Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 322

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

306
CSI/O
Cycle timing
D
Data formats
DC characteristics
DCD0 timing diagram
Description, general
Design rules, circuit board
UM005003-0703
Z8018x
Family MPU User Manual
Baud rate selection
Block diagram
Control/Status register
External clock receivetiming diagram
External clock transmit timing diagram
Internal clock receivetiming diagram
Internal clock transmit timing diagram
interrupt request generation
Operation
Receive/Transmit timing diagram
Timer initialization, count down and reload
Timer output control
Timer output timing diagram
Absolute maximum ratings
Z80180
Z8L180
Z8S180
160, 161, 172
154
153
timing diagram
186
187
189
87
131
151
146
1
139
150
163
163
170
147, 150, 159,
185
151
164
204
155
156
Direct register bit field definitions
Divide ratio
DMA
DMAC
DRAM refresh intervals
Dynamic RAM refresh control
E
E clock
Controller (DMAC)
CYCLE STEAL mode timing diagram
Edge-sense timing diagram
Interrupt request generation
Level-sense timing diagram
Mode register (DMODE)
Operation
Status register (DSTAT)
TEND0 output timing diagram
Transfer request
WAIT control register
Block diagram
Register
BUS RELEASE, SLEEP and SYSTEM
Memory and I/O R/W cycles timing dia-
Minimum timing example of PWEL and
Timing conditions
Timing diagram (R/W and INTACK cy-
106
STOP modes timing diagram
gram
PWEH timing diagram
134
93
201
104
92
110
166
89
90
100
95
97
86
108
202
114
107
181
108
201