Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 49

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

34
UM005003-0703
Z8018x
Family MPU User Manual
•
SLEEP mode is exited in one of two ways as described below.
•
•
In case of NMI, SLEEP mode is exited and the CPU begins the normal
NMI interrupt response sequence.
In the case of all other interrupts, the interrupt response depends on the
state of the global interrupt enable flag IEF1 and the individual interrupt
source enable bit.
If the individual interrupt condition is disabled by the corresponding
enable bit, occurrence of that interrupt is ignored and the CPU remains in
the SLEEP mode.
Assuming the individual interrupt condition is enabled, the response to
that interrupt depends on the global interrupt enable flag (IEF1). If
interrupts are globally enabled (IEF1 is
interrupt occurs, SLEEP mode is exited and the appropriate normal
interrupt response sequence is executed.
If interrupts are globally disabled (IEF1 is
interrupt occurs, SLEEP mode is exited and instruction execution begins
with the instruction following the SLP instruction. This feature provides a
technique for synchronization with high speed external events without
incurring the latency imposed by an interrupt response sequence.
Figure 21 depicts SLEEP timing.
Data Bus, 3-state
RESET Exit from SLEEP mode. If the RESET input is held Low for
at least six clock cycles, it exits SLEEP mode and begins the normal
RESET sequence with execution starting at address (logical and
physical)
Interrupt Exit from SLEEP mode. The SLEEP mode is exited by
detection of an external (NMI, INT0, INT2) or internal (ASCI,
CSI/O, PRT) interrupt.
00000H
.
1
) and an individually enabled
0
) and an individually enabled