Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 37

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

22
UM005003-0703
MREQ
Z8018x
Family MPU User Manual
A0
WAIT
WR
RD
D0
Phi
–
–
A19
D7
T1
Figure 12.
I/O Read/Write Timing
I/O Read/Write operations differ from memory Read/Write operations in
the following three ways:
•
•
•
At least one Wait State (TW) is always inserted for I/O read and write
cycles (except internal I/O cycles).
Figure 13 illustrates I/O read/write timing with the automatically inserted
Wait State (TW).
The IORQ (I/O Request) signal is asserted Low instead of the MREQ
signal
The 16-bit I/O address is not translated by the MMU
A16–A19 are held Low
T2
Read Cycle
Memory Read/Write (with Wait State) Timing Diagram
TW
Read data
T3
T1
T2
Write Cycle
Write data
TW
T3