Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 272
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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Table 51.
UM005003-0703
Instruction
DJNZ j
(If Br ¹ 0)
DJNZ j
(If Br=0)
EI*3
EX DE, HL
EXX
EX AF, AF’
EX (SP), HL
*2 DMA,REFRESH, or BUS RELEASE cannot be executed after this state. (Request is ignored)
*3 Interrupt request is not sampled.
Z8018x
Family MPU User Manual
Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
MC1
MC2
MC3
MC4~M
C5
MC1
MC2
MC3
MC1
MC1
MC1
MC2
MC1
MC2
MC3
MC4
MC5
MC6
States
T1T2T3
Ti*2
T1T2T3
TiTi
T1T2T3
Ti*1
T1T2T3
T1T2T3
T1T2T3
T1T2T3
Ti
T1T2T3
T1T2T3
T1T2T3
Ti
T1T2T3
T1T2T3
Address
1st Op Code
Address
*
1st operand
Address
*
1st Op Code
Address
*
1st operand
Address
1st Op Code
Address
1st Op Code
Address
1st Op Code
Address
*
1st Op Code
Address
SP
SP+1
*
SP+1
SP
Data
1st Op
Code
Z
j-2
Z
1st Op
Code
Z
j-2
1st Op
Code
1st Op
Code
1st
Z
1st Op
Code
DATA
DATA
Z
H
L
Op Code
RD WR MREQ
0
1
0
1
0
1
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
IORQ M1 HALT ST
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
0
0
0
1
0
1
1
1
1
1
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