Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 41
![IC 10MHZ Z180 CMOS ENH MPU 64DIP](/photos/6/76/67665/z8018010psg_sml.jpg)
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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26
UM005003-0703
Z8018x
Family MPU User Manual
BUSREQ
BUSACK
RD, WR
A0
D0
MREQ
IORQ
When the bus is released, the address (A0–A19), data (D0–D7), and
control (MREQ, IORQ, RD, and WR) signals are placed in the high
impedance state.
Dynamic RAM refresh is not performed when the Z8X180 has released
the bus. The alternate bus master must provide dynamic memory
refreshing if the bus is released for long periods of time.
Figure 16 illustrates BUSREQ/BUSACK bus exchange during a memory
read cycle. Figure 17 illustrates bus exchange when the bus release is
requested during a Z8X180 CPU internal operation. BUSREQ is sampled
at the falling edge of the system clock prior to T3, T1 and Tx (BUS
RELEASE state). If BUSREQ is asserted Low at the falling edge of the
clock state prior to Tx, another Tx is executed.
Figure 16.
–
–
A19
Phi
D7
T1
Bus Exchange Timing During Memory Read
CPU memory read cycle
T2
TW
T3
TX
Bus release cycle
TX
T1
CPU cycle
T1
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