MC68SEC000AA16 Freescale Semiconductor, MC68SEC000AA16 Datasheet - Page 105

• Manufacturer Part Number: MC68SEC000AA16
• Description: IC MPU 32BIT 16MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68SEC000AA16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 64-QFP
• Processor Series: M680xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Cpu Speed: 16MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 64
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Frequency Typ: 20MHz
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 16MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 7
Serial Communications Interface (SCI)
7.1 Introduction
The serial communications interface (SCI) is a universal asynchronous receiver transmitter (UART), one
of two independent serial input/output (I/O) subsystems in the M68HC11 E series of microcontrollers. It
has a standard non-return-to-zero (NRZ) format (one start bit , eight or nine data bits, and one stop bit).
Several baud rates are available. The SCI transmitter and receiver are independent, but use the same
data format and bit rate.
All members of the E series contain the same SCI, with one exception. The SCI system in the
MC68HC11E20 and MC68HC711E20 MCUs have an enhanced SCI baud rate generator. A divide-by-39
stage has been added that is enabled by an extra bit in the BAUD register. This increases the available
SCI baud rate selections. Refer to
7.2 Data Format
The serial data format requires these conditions:
Selection of the word length is controlled by the M bit of SCI control register (SCCR1).
7.3 Transmit Operation
The SCI transmitter includes a parallel transmit data register (SCDR) and a serial shift register. The
contents of the serial shift register can be written only through the SCDR. This double buffered operation
allows a character to be shifted out serially while another character is waiting in the SCDR to be
transferred into the
serial shift register. The output of the serial shift register is applied to TxD as long as transmission is in
progress or the transmit enable (TE) bit of serial communication control register 2 (SCCR2) is set. The
block diagram,
figure.
Freescale Semiconductor
1. An idle line in the high state before transmission or reception of a message
2. A start bit, logic 0, transmitted or received, that indicates the start of each character
3. Data that is transmitted and received least significant bit (LSB) first
4. A stop bit, logic 1, used to indicate the end of a frame. A frame consists of a start bit, a character
5. A break, defined as the transmission or reception of a logic 0 for some multiple number of frames
of eight or nine data bits, and a stop bit.
Figure
7-1, shows the transmit serial shift register and the buffer logic at the top of the
Figure 7-8
M68HC11E Family Data Sheet, Rev. 5.1
and
7.7.5 Baud Rate
Register.
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