MC68SEC000AA16 Freescale Semiconductor, MC68SEC000AA16 Datasheet - Page 145

IC MPU 32BIT 16MHZ 64-QFP

MC68SEC000AA16

Manufacturer Part Number
MC68SEC000AA16
Description
IC MPU 32BIT 16MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
M68000r
Datasheets

Specifications of MC68SEC000AA16

Processor Type
M680x0 32-Bit
Speed
16MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
64-QFP
Processor Series
M680xx
Core
CPU32
Maximum Clock Frequency
16 MHz
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Core Size
32 Bit
Cpu Speed
16MHz
Digital Ic Case Style
QFP
No. Of Pins
64
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Frequency Typ
20MHz
Filter Terminals
SMD
Rohs Compliant
Yes
Clock Frequency
16MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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9.7.1 Pulse Accumulator Control Register
Four of this register’s bits control an 8-bit pulse accumulator system. Another bit enables either the OC5
function or the IC4 function, while two other bits select the rate for the real-time interrupt system.
DDRA7 — Data Direction for Port A Bit 7
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
DDRA3 — Data Direction for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5 Bit
RTR[1:0] — RTI Interrupt Rate Select Bits
Freescale Semiconductor
Refer to
This bit has different meanings depending on the state of the PAMOD bit, as shown in
Refer to
Refer to
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
0 = Event counter
1 = Gated time accumulation
0 = Output compare 5 function enable (no IC4)
1 = Input capture 4 function enable (no OC5)
Chapter 6 Parallel Input/Output (I/O)
Chapter 6 Parallel Input/Output (I/O)
9.5 Real-Time Interrupt
Address:
Reset:
Read:
Write:
Figure 9-25. Pulse Accumulator Control Register (PACTL)
DDRA7
$1026
PAMOD
Bit 7
0
0
0
1
1
Table 9-7. Pulse Accumulator Edge Control
PAEN
6
0
PEDGE
M68HC11E Family Data Sheet, Rev. 5.1
(RTI).
0
1
0
1
PAMOD
5
0
PAI falling edge increments the counter.
PAI rising edge increments the counter.
A 0 on PAI inhibits counting.
A 1 on PAI inhibits counting.
PEDGE
Ports.
Ports.
4
0
Action on Clock
DDRA3
3
0
I4/O5
2
0
RTR1
1
0
RTR0
Bit 0
Pulse Accumulator
0
Table
9-7.
145

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