PSB21383HV13XT Infineon Technologies, PSB21383HV13XT Datasheet - Page 122

• Manufacturer Part Number: PSB21383HV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21383HV13XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Data Sheet
3.3.2
The transmission of transparent frames (XTF command) is shown in figure 67.
For transparent frames, the whole frame including address and control field must be
written to the XFIFO. The host configures whether the CRC is generated and appended
to the frame (default) or not (selected in EXMR.XCRC).
Furthermore, the host selects the interframe time fill signal which is transmitted between
HDLC frames (EXMR:ITF). One option is to send continuous flags (’01111110’),
however if D-channel access handling is required, the signal must be set to idle
(continuous ’1’s are transmitted).
Figure 67
Transmit Data Flow
3.4
By setting the enable HDLC data bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR register
the HDLC controller can access the D, B1, B2 channels or the combination of them (e.g.
18 bit IDSL data (2B+D)). In all modes sending works always frame aligned, i.e. it starts
with the first selected channel whereas reception looks for a flag anywhere in the serial
data stream.

Transmit Frame Structure
Access to IOM Channels
FLAG
ADDR
112
CTRL
I
CRC

HDLC Controller
PSB 21381/2
PSB 21383/4
fifoflow_tran.vsd
FLAG
2001-03-12