PSB21383HV13XT Infineon Technologies, PSB21383HV13XT Datasheet - Page 78

• Manufacturer Part Number: PSB21383HV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21383HV13XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Data Sheet
The clock pulses will be enabled again when the DU line is pulled low (e.g. bit SPU in
the IOM_CR register) or when a non-zero level on the line interface is detected and
TR_CONF0.LDD is set to ’0’. The clocks are turned on after approximately 0.2 to 4 ms
depending on the capacitances on XTAL 1/2.
DCL is activated such that its first rising edge occurs with the beginning of the bit
following the C/I (C/I0) channel.
After the clocks have been enabled this is indicated by the PU code in the C/I channel
and by a CIC interrupt. The DU line may be released by resetting the Software Power
Up bit IOM_CR.SPU = ’0’ and the C/I code written to CIX0 before (e.g. TIM or AR8) is
output on DU.
The SCOUT supplies IOM timing signals as long as there is no DIU command in the C/
I (C/I0) channel. If timing signals are no longer required and activation is not yet
requested, this is indicated by programming DIU in the CIX0 register.
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PSB 21381/2
PSB 21383/4
Interfaces
2001-03-12