PSB21383HV13XT Infineon Technologies, PSB21383HV13XT Datasheet - Page 211

• Manufacturer Part Number: PSB21383HV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21383HV13XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

LP_A
The setting of this bit corresponds to the C/I command ARL.
0: Analog loop is open
1: Analog loop is closed internally or externally according to the EXLP bit of the
7.2.6
Value after reset: 40
SQRR
MSYN
0: The S/T receiver has not yet synchronized to the multi-frame (see chapter 2.3.3)
1: The S/T receiver has synchronized to the multi-frame
MFEN
Read-back of the MFEN bit of register SQXR
SQR1-4
Received S bits of frames 1, 6, 11 and 16 of the multi-frame (see chapter 2.3.3)
7.2.7
Value after reset: 4F
SQXR
MFEN
Used to enable multi-framing (see chapter 2.3.3)
0: S/T multi-framing is disabled
1: S/T multi-framing is enabled
SQX1-4
Q bits to be transmitted at F
chapter 2.3.3)
Data Sheet
TR_CONF0 register
SQRR- S/Q-Channel Receive Register
SQXR- S/Q-channel Transmit Register
MSYN MFEN
7
7
0
... Loop Analog
... Multi-Frame Synchronization State
... Multi-Frame Enable
... Received S Bits
... Multi-Frame Enable
... Q Bits to be transmitted
MFEN
H
H
A
bit position of frames 1, 6, 11 and 16 of the multi-frame (see
0
0
0
0
201
SQR1 SQR2 SQR3 SQR4
SQX1 SQX2 SQX3 SQX4
Detailed Register Description
0
0
PSB 21381/2
PSB 21383/4
2001-03-12
WR (35
RD (35
H
H
)
)