PSB21383HV13XT Infineon Technologies, PSB21383HV13XT Datasheet - Page 208

• Manufacturer Part Number: PSB21383HV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21383HV13XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Data Sheet
LDD
0: Clock generation after detection of any signal on the line in the power down state
1: No clock generation after detection of any signal on the line in the power down state
Note: If an interrupt is generated by the internal level detect circuitry, the microcontroller
7.2.2
Value after reset: 07
TR_
CONF1
EN_SFSC
0: No short FSC is generated
1: A short FSC with a pulse length of 1 DCL is generated once per multi-frame (each
7.2.3
Value after reset: 80
TR_
CONF2
DIS_TX
The transmitter of the transceiver can be disabled or enabled by setting DIS_TX. This
can be used to make the internal Loop_A transparent (DIS_TX = ’0’) or not
(DIS_TX = ’1’) (see chapter 2.3.10.1).
0: Transmitter is enabled
1: Transmitter is disabled
PDS
Defines the phase deviation of the transmitter (see chapter 2.3.5)
0: The phase deviation is two S-bits - 2 oscillator periods plus analog delay plus delay
1: The phase deviation is two S-bits - 4 oscillator periods plus analog delay plus delay
if bit CFS of register MODE1 is set to’1’
of the external circuitry
of the external circuitry
has to set this bit to ’0’ for an activation of the line interface.
TR_CONF1 - Receiver Configuration Register
TR_CONF2 - Transmitter Configuration Register
7
7
DIS_
TX
0
... Level Detection Discard
... Enable Short FSC
... Disable Line Driver
... Phase Deviation Selection
PDS
H
H
0
SFSC
EN_
0
0
198
0
0
1
0
Detailed Register Description
1
0
0
0
1
0
PSB 21381/2
PSB 21383/4
RD/WR (31
RD/WR (32
2001-03-12
H
H
)
)