PSB21383HV13XT Infineon Technologies, PSB21383HV13XT Datasheet - Page 169

• Manufacturer Part Number: PSB21383HV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21383HV13XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 87
CRAM Access Structure
Figure 88
Signal Flow of the Back-up Procedure
Data Sheet
Data Flow
Access
µC
Write:
CCR.DCA = ’1’
CCR.SBP = ’1’
CCR.CBADR = ’x’’
Start back-up procedure block x
DSP access to temp. CRAM block
as soon as transfer has completed
Read CSR.BSYB
Back-up procedure busy?
- µC access to CRAM possible
- Switching the DSP access
Write <Block X>
Update CRAM block x
Write CCR.DCA = ’0’
DSP access to CRAM block x
between CRAM and temporary
CRAM block is possible by DCA
Temporary CRAM
<CBADR_1>
<CBADR_F>
<CBADR_E>
<CBADR_4>
<CBADR_3>
<CBADR_0>
<CBADR_D>
<CBADR_C>
<CBADR_B>
<CBADR_A>
<CBADR_9>
<CBADR_8>
<CBADR_7>
<CBADR_6>
<CBADR_5>
<CBADR_2>
Transfer not busy
159
DCA = ’0’
DCA = ’1’
Transfer busy
Access
DSP
PSB 21381/2
PSB 21383/4
2001-03-12
Codec