PSB21383HV13XT Infineon Technologies, PSB21383HV13XT Datasheet - Page 82

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PSB21383HV13XT

Manufacturer Part Number
PSB21383HV13XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21383HV13XT

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
Data Sheet
2.3.2
Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data
(B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see figure 45).
In the direction TE
framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the
standard frame structure for both directions (NT
and maintenance bits.
Frame Structure
NT the frame is transmitted with a two bit offset. For details on the
72
TE and TE
NT) with all framing
PSB 21381/2
PSB 21383/4
Interfaces
2001-03-12

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