PSB21383HV13XT Infineon Technologies, PSB21383HV13XT Datasheet - Page 196

• Manufacturer Part Number: PSB21383HV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21383HV13XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Data Sheet
RAC
The HDLC receiver is activated when this bit is set to ’1’. If it is ’0’ the HDLC data is not
evaluated in the receiver.
DIM2-0
These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit
enables/disables the collision detection. The DIM1 bit enables/disables the TIC bus
access. The effect of the individual DIM bits is summarized in table 27.
Table 27
IOM
7.1.8
Value after reset: 00
EXMR
XFBS
0: Block size for the transmit FIFO data is 32 byte
1: Block size for the transmit FIFO data is 16 byte
Note: A change of XFBS will take effect after a transmitter command (CMDR.XME,
DIM2
0
0
0
0
1
®
-2 Terminal Modes
CMDR.XRES, CMDR.XTF) has been written
DIM1
0
1
x
x
x
EXMR- Extended Mode Register
7
XFBS
DIM0
... Receiver Active
... Digital Interface Modes
… Transmit FIFO Block Size
0
1
x
x
x
H
Characteristics
Transparent D-channel, the collision detection is disabled
Stop/go bit evaluated for D-channel access handling
Last octet of IOM channel 2 used for TIC bus access
TIC bus access is disabled
Reserved
RFBS
SRA XCRC RCRC
186
Detailed Register Description
0
0
ITF
PSB 21381/2
PSB 21383/4
RD/WR (23
2001-03-12
H
)