PSB21383HV13XT Infineon Technologies, PSB21383HV13XT Datasheet - Page 212

• Manufacturer Part Number: PSB21383HV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21383HV13XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Data Sheet
7.2.8
Value after reset: 00
ISTATR
For all interrupts in the ISTATR register following logical states are defined:
0: Interrupt is not activated
1: Interrupt is activated
x
LD
Any receive signal has been detected on the line. This bit is active as long as any receive
signal is detected on the line
RIC
Any bit of register TR_STA has changed. This bit is reset by reading this register
SQC
A change in the received 4-bit S-channel (contents of one multi-frame, see
chapter 2.3.3) has been detected. The new code can be read out from the SQRx bits of
register SQRR within the next 18 S-frames (4.5 ms). This bit is reset by a read access
to the SQRR register
SQW
The S/Q channel data for the next multi-frame is writable (see chapter 2.3.3).
The register for the Q (S) bits to be transmitted (having received) has to be written (read)
within the next 18 multi-frames (4.5 ms). This bit is reset by writing register SQXR
ISTATR - Interrupt Status Register Transceiver
7
0
... Reserved
... Level Detection
... Receiver INFO Change
... S/Q Channel Change
... S/Q Channel Writable
H
x
x
x
202
LD
RIC
Detailed Register Description
SQC
0
SQW
PSB 21381/2
PSB 21383/4
2001-03-12
RD (38
H
)