PSB21383HV13XT Infineon Technologies, PSB21383HV13XT Datasheet - Page 184

• Manufacturer Part Number: PSB21383HV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21383HV13XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Data Sheet
7
The register mapping is shown in Figure 92.
Figure 92
Register Mapping
The register address range from 00-1F
address range. The address range 20-2F
handler. The register set ranging from 30-3F
general configuration registers. The address range from 40-59
handler with the registers for timeslot and data port selection (TSDP) and the control
registers (CR) for the codec data (CO), transceiver data (TR), Monitor data (MON),
HDLC/CI data (HCI) and controller access data (CDA), serial data strobe signal (SDS),
IOM interface (IOM) and synchronous transfer interrupt (STI). The address range from
5C-5F
codec coefficient RAM (CRAM) are assigned to the address range 60-6F
respectively.
The register summaries are shown in the following tables containing the abbreviation of
the register name and the register bits, the register address, the reset values and the
register type (Read/Write). A detailed register description follows these register
summaries. The register summaries and the description are sorted in ascending order
of the register address.
H
pertains to the MONITOR handler. The codec configuration registers and the
Detailed Register Description
FF
80
70
60
40
30
20
00
H
H
H
H
H
H
H
H
Transc., Interrupt, Mode Reg.
Codec Coefficient RAM
Reserved
Codec Configuration
IOM Handler (CDA, TSDP,
CR, STI), MONITOR Register
HDLC Control, CI Reg.
HDLC RFIFO/XFIFO
H
is assigned to the two FIFOs having an identical
H
174
pertains to the HDLC controller and the CI
H
pertains to the transceiver, interrupt and
Detailed Register Description
H
is assigned to the IOM
PSB 21381/2
PSB 21383/4
H
2001-03-12
or 80-FF
H