CX28229G-14 Mindspeed Technologies, CX28229G-14 Datasheet - Page 133

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CX28229G-14

Manufacturer Part Number
CX28229G-14
Description
ATM IMA 800Mbps 1.8V/3.3V 256-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet

Specifications of CX28229G-14

Package
256BGA
Utopia Type
Level 2
Typical Operating Supply Voltage
1.8|3.3 V
Minimum Operating Supply Voltage
1.71|3 V
Maximum Operating Supply Voltage
1.89|3.6 V
Maximum Output Rate
800 Mbps

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CX28229G-14
Manufacturer:
MNDSPEED
Quantity:
16
CX28224/5/9 Data Sheet
28229-DSH-001-D
FOOTNOTE:
(1)
(2)
(3)
Bit
This bit is cleared when this register is read in any of the eight ports.
Single event—A 1 to 0 transition on the corresponding pin causes this interrupt to occur, provided that this interrupt has been
enabled by the corresponding enable bit. Reading this interrupt register clears this interrupt.
This bit is a summary indication of any interrupt events that occurred in the indicated registers. This bit is a pointer to the next
interrupt indication register to be read. This bit will be cleared when the interrupt bits in the corresponding interrupt indication
registers are read and automatically cleared.
7
6
5
4
3
2
1
0
Default
0
0
0
0
0x00—SUMINT (Summary Interrupt Indication Status Register)
OneSecInt
TxCellInt
RxCellInt
The SUMINT register indicates the one-second interrupts, external framer interrupts,
and port summary interrupts.
Name
(3)
(3)
(1)
Mindspeed Technologies
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
When a logical 1 is read, this bit indicates a One Second Interrupt. This interrupt
signifies that a rising edge occurred on the OneSecIO pin (pin R5). This interrupt is
generated for each rising edge on the OneSecIO pin.
Reserved, set to a logical 0.
When a logical 1 is read, this bit indicates a Transmit Cell Interrupt. This interrupt is
a summary interrupt and signifies that an interrupt indication occurred in the
TxCellInt register (0x2C).
When a logical 1 is read, this bit indicates a Receive Cell Interrupt. This interrupt is a
summary interrupt and signifies that an interrupt indication occurred in the
RxCellInt register (0x2D).
Description
Registers
7
-
33

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