CX28229G-14 Mindspeed Technologies, CX28229G-14 Datasheet - Page 54

• Manufacturer Part Number: CX28229G-14
• Description: ATM IMA 800Mbps 1.8V/3.3V 256-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CX28229G-14

• Package: 256BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3 V
• Maximum Operating Supply Voltage: 1.89|3.6 V
• Maximum Output Rate: 800 Mbps

CX2822x Hardware Description
Table 2-5. CX28229 Pin Descriptions (5 of 12)
2-26
TRST*
TCK
TMS
TDI
TDO
TestEnable
TestMode
PhyIntFcSel
phyURxEnb[1]*
phyUTxAddr[0]
phyUTxAddr[3]
phyUTxAddr[4]
phyUTxEnb[0]*
phyUTxEnb[1]*
IMA_SysClk
IMA_RefClk
TxTRL[0]
TxTRL[1]
Pin Label
Test Reset
Test Clock
Test Mode Select
Test Data Input
Test Data Output
PHY Interface Select
PHY UTOPIA Receive
Enable
PHY UTOPIA
Transmit Address
PHY UTOPIA
Transmit Enable
IMA Subsystem
Clock
IMA Subsystem
Clock
Transmit Reference
Clock
Signal Name
Mindspeed Technologies
M16
No.
E13
E14
L14
F13
F16
F15
R4
NC
NC
NC
NC
NC
NC
T3
T4
P4
A3
I/PU
I/PU
I/PU
I/O
O
O
O
O
O
I
I
I
I
I
I
When asserted, the internal boundary-scan logic is reset.
This pin has a pull-up resistor.
Note: In accordance with the IEEE 1149.1 specification, it
is recommended that TRST* be held low until power is
stable in order to ensure deterministic operation. This can
be done by connecting the TRST* pin to the Reset* pin.
Note: When JTAG is not used, this pin should be tied either
directly to ground or though a 1K or less pull down
resistor.
Samples the value of TMS and TDI on its rising edge to
control the boundary scan operations.
Controls the boundary-scan Test Access Port (TAP)
controller operation. This pin has a pull-up resistor.
The serial test data input. This pin has a pull-up resistor.
The serial test data output.
Factory test use only, tie to VSS.
Factory test use only, tie to VSS.
If this pin is tied low, the PHY UTOPIA Interface mode is
selected.
If this pin is tied high, the PHY Serial mode is selected (as
shown in this table).
This pin is a No Connect when PhyIntFcSel is tied high.
These pins are a No Connect when PhyIntFcSel is tied high.
These pins are a No Connect when PhyIntFcSel is tied high.
Most of the IMA logic circuits use this clock (or a derivative
of it). It can also be used as a T1/E1 reference clock. Refer
to
If Ref_Xclk is to be used as a reference clock, set the
frequency as shown in
Transmit Reference Clocks.
Chapter
3.
™
Description
Chapter
3.
CX28224/5/9 Data Sheet
28229-DSH-001-D