CX28229G-14 Mindspeed Technologies, CX28229G-14 Datasheet - Page 135

• Manufacturer Part Number: CX28229G-14
• Description: ATM IMA 800Mbps 1.8V/3.3V 256-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CX28229G-14

• Package: 256BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3 V
• Maximum Operating Supply Voltage: 1.89|3.6 V
• Maximum Output Rate: 800 Mbps

CX28224/5/9 Data Sheet
28229-DSH-001-D
FOOTNOTE:
(1)
Bit
These bits should only be changed when the device or port logic reset is asserted.
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0x04—PMODE (Port Mode Control Register)
PrtMstRst
PrtLgcRst
SrcLoop
FeLnLoop
PhyType[2]
PhyType[1]
PhyType[0]
The PMODE register controls the port-level software resets, source loopback, and
physical layer interface mode.
Name
(1)
—
(1)
(1)
(1)
(1)
Mindspeed Technologies
When written to a logical 1, this bit initiates a Port Master Reset. All internal state
machines associated with this port are reset and all control registers for this port,
except this one, assume their default values. Only bits 0–6 in this register are
overwritten with their default values.
When written to a logical 1, this bit initiates a Port Logic Reset. All internal state
machines associated with this port are reset but all registers (0x00–0x3F) listed as
“Type: W/R” in
during Port Logic Reset.
When written to a logical 1, this bit enables a source loopback. The line transmit
clock and data outputs are connected to the line receive clock and data inputs. Refer
to
General Purpose mode (ignoring the contents of the PhyType[2:0] bits).
Enables Far-end line loopback. In this mode, the receive data is processed by the TC
block and looped back at the UTOPIA interface to the transmit side. Refer to
Figure
Reserved, set to a logical 0.
These bits determine the Physical Layer Interface Mode:
(However, good design practice would have them tied high.)
000—T1 mode
001—E1 mode
010—Reserved
Figure
In General Purpose Mode, the SPRxSync and SPTxSync pins are ignored.
2-9.
2-8. During Source loopback, the device is automatically configured for
Table 7-3
011—Reserved
100—Reserved
101—General Purpose
are unaltered. Output signals for this port are three-state
Description
™
110—DSL Mode
111—Power Down
Registers
7
-
35