CX28229G-14 Mindspeed Technologies, CX28229G-14 Datasheet - Page 255

• Manufacturer Part Number: CX28229G-14
• Description: ATM IMA 800Mbps 1.8V/3.3V 256-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CX28229G-14

• Package: 256BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3 V
• Maximum Operating Supply Voltage: 1.89|3.6 V
• Maximum Output Rate: 800 Mbps

CX28224/5/9 Data Sheet
Table A-4. IMA Data Cell (IDC) Rate Implementation Functions
28229-DSH-001-D
IDC.1
IDC.2
IDC.3
IDC.4
IDC.5
IDC.6
IDC.7
IDC.8
IDC.9
IDC.10
IDC.11
IDC.12
IDC.13
Comments:
Item
Does the implementation ensure on transmit that a Filler cell is not
injected if an ATM layer cell is available for scheduling?
Does the implementation only check on transmit that an ATM layer
cell is available and accept that cell only when the Tx IDCC ticks?
Does the implementation only select the TRL from the set of links
whose transmit state is Active?
If there is no link in the Active state, does the implementation select
one of the links in the Usable state, if any, or one of the links in the
Unusable state otherwise?
Does the implementation only select or change the TRL during the
following situations:
during group start-up,
when the previously selected TRL's transmit state changes from
Active to any other state (e.g., Usable, Unusable, or Not In Group)
while another link’s transmit state is Active, or
when the previously selected TRL’s transmit state changes from
Usable to Unusable or Not In Group while another link’s transmit
state is Active or Usable?
Does the implementation indicate the selected or changed TRL to
the FE over the “Transmit Timing Information” field in the ICP cell?
Does the implementation derive the Tx IDCC from the selected TRL
according to Equation 1 on page 40?
When running in the CTC mode, does the implementation introduce
a stuff event every 2048 ICP, Filler and ATM layer cells on all links?
Does the implementation introduce a stuff event every 2048 ICP,
Filler and ATM layer cells on the TRL?
Does the implementation introduce stuff events on links other than
the TRL in order to compensate for the timing difference between
the TRL and the other links?
Does the implementation remove CDV attributed to the presence of
ICP cells by a mechanism equivalent to providing a small
smoothing buffer into which cells are placed after reordering and
after removing ICP cells?
If the TRL is in the Working state and the FE has, for at least 100
milliseconds, identified a given link as the TRL, does the
implementation derive the Rx IDCR using the incoming link
indicated by the FE as the TRL?
Does the implementation have an equivalent behavior to the
following: when the IMA data cell clock at the receiver ticks, one cell
is removed from the smoothing buffer; if the cell is a Filler cell, then
the Filler cell is discarded and nothing passed to the ATM layer; if
the cell is not a Filler cell, then it is passed to the ATM layer?
Protocol feature
Mindspeed Technologies
(O-9)
(O-9)
Cond. for
Status
™
Status
Pred.
M
M
M
M
M
M
M
M
M
M
M
M
M
IMA Version 1.1 PICS Proforma
(R-64)
(R-64)
(R-65)
(R-66)
(R-67)
(R-68)
(R-69)
(R-70)
(CR-5)
(CR-6)
(R-71)
(R-72)
(R-73)
Ref.
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Support
A
-
9