CX28229G-14 Mindspeed Technologies, CX28229G-14 Datasheet - Page 139

• Manufacturer Part Number: CX28229G-14
• Description: ATM IMA 800Mbps 1.8V/3.3V 256-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CX28229G-14

• Package: 256BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3 V
• Maximum Operating Supply Voltage: 1.89|3.6 V
• Maximum Output Rate: 800 Mbps

CX28224/5/9 Data Sheet
28229-DSH-001-D
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0x0B—ERRPAT (Error Pattern Control Register)
0x0C—CVAL (Cell Validation Control Register)
ErrPat[7]
ErrPat[6]
ErrPat[5]
ErrPat[4]
ErrPat[3]
ErrPat[2]
ErrPat[1]
ErrPat[0]
RejHdr
DelIdle
EnRxCos
EnRxCellScr
EnHECCorr
DisHECChk
DisCellRcvr
DisLOCD
The ERRPAT register provides the error pattern for the HEC error insertion function.
ErrHEC (bit 4) in the CGEN register (0x08) enables this function. Each bit in the error
pattern register is XORed with the corresponding bit of the calculated HEC byte to be
errored.
The CVAL register controls the validation of incoming cells.
Name
Name
Mindspeed Technologies
Error pattern bit 7.
Error pattern bit 6.
Error pattern bit 5.
Error pattern bit 4.
Error pattern bit 3.
Error pattern bit 2.
Error pattern bit 1.
Error pattern bit 0.
When written to a logical 1, this bit enables the Rejection of certain Header cells.
When enabled, cells with headers matching the RXHDRx/RXMSKx definition are
rejected and all others are accepted. When written to a logical 0, cells with matching
headers are accepted and cells with non-matching headers are rejected.
When written to a logical 1, this bit enables the Deletion of Idle Cells. When enabled,
cells matching the RXIDL/IDLMSK definition are deleted from the received cell
stream. When written to a logical 0, idle cells are included in the received stream.
When written to a logical 1, this bit enables the Receive HEC Coset. When written to
a logical 0, the HEC Coset is disabled.
When written to a logical 1, this bit enables the Receive Cell Scrambler. When
written to a logical 0, the Receive Cell Scrambler is disabled.
When written to a logical 1, this bit enables HEC Correction. When written to a
logical 0, HEC Correction is disabled.
When written to a logical 1, this bit disables HEC Checking. When written to a logical
0, HEC checking is performed as a cell validation criterion. See
When written to a logical 1, this bit disables the Cell Receiver. When disabled, all cell
reception is disabled on the next cell boundary. When written to a logical 0, cell
reception begins or resumes on the next cell boundary.
When written to a logical 1, this bit disables Loss of Cell Delineation. When disabled,
cells are passed even if cell delineation has not been found. When written to a
logical 0, cells are passed only while cell alignment has been achieved. See
Table
5-1.
Description
Description
™
Table
5-1.
Registers
7
-
39