CX28229G-14 Mindspeed Technologies, CX28229G-14 Datasheet - Page 50

• Manufacturer Part Number: CX28229G-14
• Description: ATM IMA 800Mbps 1.8V/3.3V 256-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CX28229G-14

• Package: 256BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3 V
• Maximum Operating Supply Voltage: 1.89|3.6 V
• Maximum Output Rate: 800 Mbps

CX2822x Hardware Description
Table 2-5. CX28229 Pin Descriptions (1 of 12)
2-22
StatOut[0]
StatOut[1]
MSyncMode
Reset*
8kHzIn
OneSecIO
MW/R, MRd*
MCS*
Pin Label
Status Output
Microprocessor
Synchronous/
Asynchronous Bus
Mode Select
Device Reset
8 kHz Input
One-Second Input/
Output
Microprocessor
Write/Read
Microprocessor Chip
Select
Signal Name
Mindspeed Technologies
No.
M1
M2
N5
N6
R5
P5
A2
B2
I/O
I/O
O
I
I
I
I
I
General purpose output pins under software control.
Selects synchronous or asynchronous bus mode, which
determines the functions of two pins, MW/R,MRd* (pin
A2) and MAS*,MWr* (pin A1). A logic 1 selects the
synchronous bus mode, compatible with Bt8230 and
Bt8233. In this mode, these pins are defined as follows:
MW/R (A2) and MAS* (A1). A logic 0 selects the
asynchronous SRAM-type bus mode. In this mode, the
pins are defined as follows: MRd* (A2) and MWr* (A1).
When asserted low, resets the device. The microprocessor
clock must be present before reset is released.
A clock input used to derive OneSecIO. Typically operates
at a frequency of 8 kHz.
Software can configure this pin as an output that equals
the input from the 8kHzIn divided by 8000. When
configured as an input, status registers and counters may
be latched on the rising edge of this input. See Bit 0 of the
Mode register (0x200).
When MSyncMode is asserted high, this pin is a read/write
control pin. In this mode, when MW/R is asserted high, a
write access is enabled and the MicroData[7:0] pin values
will be written to the memory location indicated by the
MicroAddr[10:0] pins. Also, when MW/R is asserted low in
this mode, a read access is enabled and the memory
location indicated by the MicroAddr[10:0] pins is read. Its
value is placed on the MicroData[7:0] pins. Both read and
write accesses assume the device is chip selected (MCS* =
0), the address is valid (MAS* = 0), and the device is not
being reset (Reset* = 1).
When MSyncMode is asserted low, this pin is a read
control pin. In this mode, when MRd* is asserted low, a
read access is enabled and the memory location indicated
by the MicroAddr[10:0] pins is read. Its value is placed on
the MicroData[7:0] pins.
When asserted low, the device is selected for read and
write accesses. When asserted high, the device will not
respond to input signal transitions on MicroClk, MW/R,
MRd*, or MAS*, MWr*. Additionally, when MCS* is
asserted high, the MicroData[7:0] pins are in a high-
impedance state but the MicroInt* pin remains operational.
™
Description
CX28224/5/9 Data Sheet
28229-DSH-001-D