CX28229G-14 Mindspeed Technologies, CX28229G-14 Datasheet - Page 140

• Manufacturer Part Number: CX28229G-14
• Description: ATM IMA 800Mbps 1.8V/3.3V 256-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CX28229G-14

• Package: 256BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3 V
• Maximum Operating Supply Voltage: 1.89|3.6 V
• Maximum Output Rate: 800 Mbps

Registers
7-40
FOOTNOTE:
(1)
FOOTNOTE:
(1)
(2)
Bit
Bit
These bits should only be changed when the device or port logic reset is asserted.
These bits should only be changed when the device or port logic reset is asserted.
The default for these bits is the port number for each port. (000—Port 0, 001—Port 1, 010—Port 2, 011—Port 3, 100—Port 4,
101—Port 5, 110—Port 6, 111—Port 7)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
(2)
(2)
(2)
0
0
0
0
0
0
0
0
0
0
x
0
0
0x0D—UTOP1 (UTOPIA Control Register 1)
0x0E—UTOP2 (UTOPIA Control Register 2) (TC Block)
TxReset
RxReset
UtopDis
MphyAddr[4]—
MSB
MphyAddr[3]
MphyAddr[2]
MphyAddr[1]
MphyAddr[0]—
LSB
(1)
(1)
The UTOP1 register controls the UTOPIA resets, parity orientation, and the transmit
FIFO fill-level threshold.
The UTOP2 register contains the multi-PHY address value for the port.
Name
Name
(1)
—
—
—
—
—
—
—
—
(1)
(1)
(1)
Mindspeed Technologies
When written to a logical 1, this bit resets the transmit FIFO pointers. This reset
should only be used as a test function because it can create short cells.
When written to a logical 1, this bit resets the receive FIFO pointers. This reset
should only be used as a test function because it can create short cells.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
When written to a logical 1, this bit disables UTOPIA outputs for this port.
These bits are the Multi-PHY Device Address. Each CX2822x port should have a
unique address. These bits correspond to the URxAddr and UTxAddr pins. When
the pin matches the bit values, the port is accessed. This port ignores any
transactions meant for another port or PHY device.
CX28229-11
CX28229-12 and later
Version
Description
™
Description
Default
0
1
CX28224/5/9 Data Sheet
28229-DSH-001-D