CX28229G-14 Mindspeed Technologies, CX28229G-14 Datasheet - Page 169

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CX28229G-14

Manufacturer Part Number
CX28229G-14
Description
ATM IMA 800Mbps 1.8V/3.3V 256-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet

Specifications of CX28229G-14

Package
256BGA
Utopia Type
Level 2
Typical Operating Supply Voltage
1.8|3.3 V
Minimum Operating Supply Voltage
1.71|3 V
Maximum Operating Supply Voltage
1.89|3.6 V
Maximum Output Rate
800 Mbps

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CX28229G-14
Manufacturer:
MNDSPEED
Quantity:
16
CX28224/5/9 Data Sheet
28229-DSH-001-D
7–6
5–4
2–0
Bit
Bit
3
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0x402—IMA_SUBSYS_CONFIG (IMA Configuration Control)
0x403—IMA_MISC_STATUS (IMA Miscellaneous Status)
Link Type
SRAM size
Number of SRAMs
Number of Ports
State of TxAddr[4]
State of RxAddr[4]
ATM Data Width
IMA_RefClk Error
Tx ATM Parity Error
Rx PHY Parity Error
This register contains some of the basic IMA Subsystem configuration.
This register contains miscellaneous status information for the IMA Subsystem.
Read-only.
Name
Name
Mindspeed Technologies
Sets default link type for all IMA groups. Not used with variable rate facilities
0 = 25 ms (E1 mode)
1 = 50 ms
2 = 100 ms
3 = 200 ms
0 = 1 SRAM, Set to 0 for all CX2822X devices
This field indicates the range of valid PHY addresses.
This field has different ranges depending on Product type:
This bit is the current state of the signal ATMUTxAddr[4].
This bit is the current state of the signal ATMURxAddr[4].
Reserved
This bit indicates whether the ATM Utopia bus is operating in 16 bit (high) or 8 bit
(low) data mode.
This bit is set high if a transition detector for IMA_RefClk detects a bad signal. This
bit is active high and is reset upon reading this address.
This bit indicates that a parity error has been detected on the Transmit ATM side
Utopia bus. This bit is active high and is reset upon reading this address.
Reserved.
This bit indicates that a parity error has been detected on the Receive PHY side cell
bus. This bit is active high and is reset upon reading this address.
0 = T1
1 = E1
2 = Alternate T1 (1.544 Mbps payload)
3 = Alternate E1 (1.984 Mbps payload)
0: addresses 0x00–0x03 are valid
1: addresses 0x00–0x07 are valid
2: addresses 0x00–0x0B are valid
3: addresses 0x00–0x0F are valid
4: addresses 0x00–0x13 are valid
5: addresses 0x00–0x17 are valid
6: addresses 0x00–0x1B are valid
7: addresses 0x00–0x1F are valid
CX28224: Unused, Set to 0
CX28225: Unused, Set to 0
CX28229: Range: 0–7
Description
Description
Registers
7
-
69

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