DS21Q58L+ Maxim Integrated Products, DS21Q58L+ Datasheet - Page 14

• Manufacturer Part Number: DS21Q58L+
• Description: IC TXRX E1 QUAD 3.3V 100LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q58L+

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

6. HOST INTERFACE PORT
The DS21Q58 is controlled through either a nonmultiplexed bus, a multiplexed bus, or serial interface bus by an
external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing
configurations. See
parentheses (). See the timing diagrams in the AC Electrical Characteristics in Section
Table 6-1. Bus Mode Select
6.1 Parallel Port Operation
When using the parallel interface on the DS21Q58 (BTS1 = 0) the user has the option for either multiplexed bus
operation (BTS1 = 0, BTS0 = 0) or nonmultiplexed bus operation (BTS1 = 0, BTS0 = 1). The DS21Q58 can operate
with either Intel or Motorola bus timing configurations. If the PBTS pin is wired low, Intel timing is selected; if wired
high, Motorola timing is selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in
Section
6.2 Serial Port Operation
Setting the BTS1 pin = 1 and BTS0 pin = 0 enables the serial bus interface on the DS21Q58. Port read/write timing
is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See
Section
Figure
Reading or writing to the internal registers requires writing one address/command byte prior to transferring register
data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write
(0). The next five bits identify the register address. The next bit is reserved and must be set to 0 for proper
operation. The last bit (MSB) of the address/command byte enables the burst mode when set to 1. The burst mode
causes all registers to be consecutively written or read.
All data transfers are initiated by driving the CS input low. When input-clock edge select (ICES) is low, input data is
latched on the rising edge of SCLK; when ICES is high, input data is latched on the falling edge of SCLK. When
output-clock edge select (OCES) is low, data is output on the falling edge of SCLK; when OCES is high, data is
output on the rising edge of SCLK. Data is held until the next falling or rising edge. All data transfers are terminated
if the CS input transitions high. Port control logic is disabled and SDO is tri-stated when CS is high.
Figure 6-1. Serial Port Operation Mode 1
PBTS
X
X
0
0
1
1
SCLK
CS
SDI
SDO
ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK)
OCES = 1 (UPDATE SDO ON THE RISING EDGE OF SCLK)
6-3, and
26
26
BTS1
R/W
for more details.
0
0
0
0
1
1
1
LSB
for the AC timing of the serial port. All serial port accesses are LSB first. See
Figure 6-4
BTS0
2
A0
0
1
0
1
0
1
Table 6-1
3
A1
for more details.
PARALLEL PORT MODE
Motorola Nonmultiplexed
TEST (Outputs High-Z)
4
A2
Motorola Multiplexed
Intel Nonmultiplexed
for a description of the bus configurations. Motorola bus signals are listed in
Intel Multiplexed
5
A3
Serial
6
A4
7
A5
14 of 74
MSB
8
B
9
D0
LSB
10
D1
11
D2
12
D3
13
D4
26
for more details.
14
D5
Figure
15
D6
6-1,
MSB
16
D7
Figure
6-2,