DS21Q58L+ Maxim Integrated Products, DS21Q58L+ Datasheet - Page 35

• Manufacturer Part Number: DS21Q58L+
• Description: IC TXRX E1 QUAD 3.3V 100LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q58L+

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

10.3 E-Bit/PRBS Bit-Error Counter
E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit
counter that records far-end block errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running
with CRC4 multiframe. These error count registers increment once each time the received E-bit is set to 0. Since
the maximum E-bit count in a one-second period is 1000, this counter cannot saturate. The counter is disabled
during loss of sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the
CAS level.
Alternately, this counter counts bit errors in the received PRBS pattern when the receive PRBS function is enabled.
In this mode, the counter is active when the receive PRBS detector can synchronize to the PRBS pattern. This
pattern can be framed, unframed, or in any time slot. See Section
Register Name:
Register Description:
Register Address:
Bit #
Name
10.4 FAS Error Counter
FAS count register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 16-bit
counter that records word errors in the FAS in time slot 0. This counter is disabled when RLOS is high. FAS errors
are not counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4
multiframe level. Since the maximum FAS word error count in a one-second period is 4000, this counter cannot
saturate.
Register Name:
Register Description:
Register Address:
Bit #
Name
FAS15
NAME
NAME
EB15
FAS0
EB0
FAS15
EB15
FAS7
EB7
7
7
FASCR1.7
FASCR2.0
EBCR1.7
EBCR2.0
BIT
BIT
FAS14
FAS6
EB14
EB6
6
6
EBCR1, EBCR2
E-Bit Count Registers
04 Hex, 05 Hex
FASCR1, FASCR2
FAS Error Count Registers
06 Hex, 07 Hex
MSB of the 16-bit E-bit error count.
LSB of the 16-bit E-bit error count.
MSB of the 16-bit FAS error count.
LSB of the 16-bit FAS error count.
FAS13
FAS5
EB13
EB5
5
5
FAS12
FAS4
EB12
EB4
4
4
35 of 74
FAS11
FAS3
EB11
EB3
3
3
FUNCTION
FUNCTION
13
FAS10
EB10
FAS2
EB2
for more details.
2
2
FAS9
FAS1
EB9
EB1
1
1
FAS8
FAS0
EB8
EB0
0
0