DS21Q58L+ Maxim Integrated Products, DS21Q58L+ Datasheet - Page 29

• Manufacturer Part Number: DS21Q58L+
• Description: IC TXRX E1 QUAD 3.3V 100LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q58L+

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

Register Name:
Register Description:
Register Address:
Bit #
Name
9.2 CRC4 Sync Counter
The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared
when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by
disabling the CRC4 mode (CCR1.0 = 0). This counter is useful for determining the amount of time the framer has
been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4
level cannot be obtained within 400ms, the search should be abandoned and proper action taken. The CRC4 sync
counter rolls over.
Table 9-1. Alarm Criteria
CRC4SA
CASSA
FASSA
(Receive Unframed
NAME
(Receive Signaling
(Receive Signaling
CSC5
CSC4
CSC3
CSC2
CSC0
Multiframe Alarm)
(Receive Remote
(Receive Distant
(Receive Carrier
All Zeros)
All Ones)
All Ones)
ALARM
RDMA
Alarm)
RUA1
RSA1
RSA0
Loss)
RRA
RCL
CSC5
7
BIT
7
6
5
4
3
2
1
0
Over 16 consecutive frames (one full
MF) time slot 16 contains less than three
zeros
Over 16 consecutive frames (one full
MF) time slot 16 contains all zeros
Bit 6 in time slot 16 of frame 0 set to one
for two consecutive MF
Fewer than three zeros in two frames
(512 bits)
Bit 3 of nonalign frame set to one for
three consecutive occasions
255 (or 2048) consecutive zeros
received
CSC4
CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.
CRC4 Sync Counter Bit 4
CRC4 Sync Counter Bit 3
CRC4 Sync Counter Bit 2
CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. Counter bit 1 is not
accessible.
FAS Sync Active. Set while the synchronizer is searching for alignment at the
FAS level.
CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF
alignment word.
CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4
MF alignment word.
6
SSR
Synchronizer Status Register
09 Hex
SET CRITERIA
CSC3
5
CSC2
4
29 of 74
CSC0
FUNCTION
3
Over 16 consecutive frames (one full
MF) time slot 16 contains three or more
zeros
Over 16 consecutive frames (one full
MF) time slot 16 contains at least a
single one
Bit 6 in time slot 16 of frame 0 set to
zero for two consecutive MF
More than two zeros in two frames (512
bits)
Bit 3 of nonalign frame set to zero for
three consecutive occasions
In 255-bit times at least 32 ones are
received
FASSA
2
CLEAR CRITERIA
CASSA
1
CRC4SA
0
ITU SPEC
1.6.1.2
G.775/
G.732
G.732
O.162
O.162
O.162
G.962
2.1.5
2.1.4
4.2
5.2