DS21Q58L+ Maxim Integrated Products, DS21Q58L+ Datasheet - Page 23

• Manufacturer Part Number: DS21Q58L+
• Description: IC TXRX E1 QUAD 3.3V 100LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q58L+

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

8.5 Local Loopback
When CCR4.6 is set to 1, the DS21Q58 is forced into local loopback (LLB) mode. In this loopback, data continues
to be transmitted as normal. Data being received at RTIP and RRING is replaced with the data being transmitted.
Data in this loopback passes through the jitter attenuator
Register Name:
Register Description:
Register Address:
Bit #
Name
NAME
LIRST
RESA
RESR
RCM4
RCM3
RCM2
RCM1
RCM0
LIRST
7
BIT
7
6
5
4
3
2
1
0
RESA
Line Interface Reset. Setting this bit from 0 to 1 initiates an internal reset
that affects the clock recovery state machine and jitter attenuator.
Normally this bit is only toggled on power-up. It must be cleared and set
again for a subsequent reset.
Receive Elastic Store Align. Setting this bit from 0 to 1 may force the
receive elastic store’s write/read pointers to a minimum separation of half
a frame. No action is taken if the pointer separation is already greater
than or equal to half a frame. If pointer separation is less than half a
frame, the command is executed and data is disrupted. This bit should be
toggled after SYSCLK has been applied and is stable. It must be cleared
and set again for a subsequent align. See Section
Receive Elastic Store Reset. Setting this bit from 0 to 1 forces the
receive elastic store to a depth of one frame. Receive data is lost during
the reset. The bit should be toggled after SYSCLK has been applied and
is stable. It must be cleared and set again for a subsequent reset. See
Section
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data appears in the RDS0M register.
See Section
Receive Channel Monitor Bit 3
Receive Channel Monitor Bit 2
Receive Channel Monitor Bit 1
Receive Channel Monitor Bit 0. LSB of the channel decode.
6
CCR4
Common Control Register 4
15 Hex
18
RESR
for details.
5
10
for details.
RCM4
4
23 of 74
FUNCTION
RCM3
(Figure
3
3-1).
RCM2
2
18
for details.
RCM1
1
RCM0
0