DS21Q58L+ Maxim Integrated Products, DS21Q58L+ Datasheet - Page 42

• Manufacturer Part Number: DS21Q58L+
• Description: IC TXRX E1 QUAD 3.3V 100LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q58L+

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

17.
The DS21Q58 has per-channel loopback capability that can operate in one of two modes: remote per-channel
loopback or local per-channel loopback. PCLB1/2/3/4 are used for both modes to determine which channels are
looped back. In remote per-channel loopback mode, PCLB1/2/3/4 determine which channels (if any) in the transmit
direction should be replaced with the data from the receiver or, in other words, off the E1 line. In local per-channel
loopback mode, PCLB1/2/3/4 determine which channels (if any) in the receive direction should be replaced with the
data from the transmit. If either mode is enabled, transmit and receive clocks and frame syncs must be
synchronized. There are no restrictions on which channels can be looped back or on how many channels can be
looped back.
Register Name:
Register Description:
Register Address:
Bit #
Name
18.
The DS21Q58 contains a two-frame (512 bits) elastic store for the receive direction. The elastic store absorbs the
differences in frequency and phase between the E1 data stream and an asynchronous (i.e., not frequency locked)
backplane clock that can be 2.048MHz for normal operation or 4.096MHz, 8.192MHz, or 16.384MHz when using
the IBO function. The elastic store contains full controlled slip capability.
If the receive elastic store is enabled (RCR.4 = 1), the user must provide a 2.048MHz clock to the SYSCLK pin. If
the IBO function is enabled, a 4.096MHz, 8.192MHz, or 16.384MHz clock must be provided at the SYSCLK pin.
The user has the option of either providing a frame/multiframe sync at the RSYNC pin (RCR.5 = 1) or having the
RSYNC pin provide a pulse on frame/multiframe boundaries (RCR.5 = 0). If the user wishes to obtain pulses at the
frame boundary, RCR1.6 must be set to 0; if the user wishes to have pulses occur at the multiframe boundary,
RCR1.6 must be set to 1. If the elastic store is enabled, either CAS (RCR.7 = 0) or CRC4 (RCR.7 = 1) multiframe
boundaries are indicated through the RSYNC output. See Section
either fills or empties, a controlled slip occurs. If the buffer empties, a full frame of data (256 bits) is repeated at
RSER, and the SR1.4 and RIR.3 bits are set to 1. If the buffer fills, a full frame of data is deleted, and the SR1.4
and RIR.4 bits are set to 1.
CH1 to CH32
NAME
PER-CHANNEL LOOPBACK
ELASTIC STORE OPERATION
CH16
CH24
CH32
CH8
7
PCLB1.0 to 4.7
CH15
CH23
CH31
CH7
6
PCLB1, PCLB2, PCLB3, PCLB4
Per-Channel Loopback Registers
2B Hex, 2C Hex, 2D Hex, 2E Hex
BIT
CH14
CH22
CH30
CH6
5
Per-Channel Loopback Control Bits
0 = do not loopback this channel
1 = loopback this channel
CH13
CH21
CH29
CH5
4
42 of 74
CH12
CH20
CH28
CH4
3
FUNCTION
24
CH11
CH19
CH27
CH3
2
for timing details. If the 512-bit elastic buffer
CH10
CH18
CH26
CH2
1
CH17
CH25
CH1
CH9
0