DS21Q58L+ Maxim Integrated Products, DS21Q58L+ Datasheet - Page 27

• Manufacturer Part Number: DS21Q58L+
• Description: IC TXRX E1 QUAD 3.3V 100LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q58L+

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

DS21Q58 E1 Quad Transceiver
9. STATUS AND INFORMATION REGISTERS
The DS21Q58 has a set of four registers that contain information about a framer’s real-time status. The registers
include status register 1 (SR1), status register 2 (SR2), receive information register (RIR), and synchronizer status
register (SSR).
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers is set to 1.
All the bits in the SR1, SR2, and RIR1 registers operate in a latched fashion. The SSR contents are not latched,
which means that if an event or an alarm occurs and a bit is set to 1 in any of the registers, the bit remains set until
the user reads that bit. The bit is cleared when it is read and is not set again until the event has occurred again (or,
in the case of the RUA1, RRA, RCL, and RLOS alarms, the bit remains set if the alarm is still present).
The user always precedes a read of the SR1, SR2, and RIR registers with a write. The byte written to the register
informs the framer which bits the user wishes to read and have cleared. The user writes a byte to one of these
registers with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to
obtain the latest information on. When a 1 is written to a bit location, the read register updates with the latest
information. When a 0 is written to a bit position, the read register does not update and the previous value is held.
A write to the status and information registers is immediately followed by a read of the same register. The read
result should be logically ANDed with the mask byte that was just written, and this value should be written back into
the same register to ensure the bit clears. This second write step is necessary because the alarms and events in
the status registers occur asynchronously in respect to their access through the parallel port. This write-read-write
scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the
other bits in the register. This operation is key in controlling the DS21Q58 with higher-order software languages.
The SSR register operates differently than the other three. It is a read-only register and reports the status of the
synchronizer in real time. This register is not latched and it is not necessary to precede a read of this register with a
write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt through the INT output pin. Each
of the alarms and events in SR1 and SR2 can be either masked or unmasked from the interrupt pin through
interrupt mask register 1 (IMR1) and interrupt mask register 2 (IMR2).
The interrupts caused by alarms in SR1 (RUA1, RRA, RCL, and RLOS) act differently than the interrupts caused
by events in SR1 and SR2 (RSA1, RDMA, RSA0, RSLIP, RMF, TMF, SEC, TAF, LOTC, and RCMF). The alarm-
caused interrupts force the INT pin low whenever the alarm changes state (i.e., the alarm goes active or inactive
9-1). The INT pin is allowed to return high (if no other interrupts are
according to the set/clear criteria in
Table
present) when the user reads the alarm bit that caused the interrupt to occur, even if the alarm is still present.
The event-based interrupts force the INT pin low when the event occurs. The INT pin returns high () when the user
reads the event bit that caused the interrupt to occur. Furthermore, some event-based interrupts occur continuously
as long as the event is occurring (RSLIP, SEC, TMF, RMF, TAF, RAF, RCMF). Other event-based interrupts force
the INT pin low only once when the event is first detected (LOTC, PRSBD, RDMA, RSA1, RSA0), that is, the
PRBSD interrupt fires once when the receiver detects the PRBS pattern. If the receiver continues to receive the
PRBS pattern, no more interrupts are fired. If the receiver then detects that PRBS is no longer being sent, it resets
and, when it receives the PRBS pattern again, another interrupt is fired.
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