DS21Q58L+ Maxim Integrated Products, DS21Q58L+ Datasheet - Page 28

• Manufacturer Part Number: DS21Q58L+
• Description: IC TXRX E1 QUAD 3.3V 100LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q58L+

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

9.1 Interrupt Handling
The host can quickly determine which status registers in the four ports are causing an interrupt by reading one of
the unused addresses such as 0Ch, 0Dh, or 0Eh in any port.
Bit #
Name
Register Name:
Register Description:
Register Address:
Bit #
Name
CRCRC
CASRC
FASRC
SR2P4
SR1P4
SR2P3
SR1P3
SR2P2
SR1P2
SR2P1
SR1P1
NAME
NAME
RESE
RESF
JALT
—
—
SR2P4
—
7
7
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SR1P4
Status Register 2, Port 4. A 1 in this bit position indicates that status register 2
in port 4 is asserting an interrupt.
Status Register 1, Port 4. A 1 in this bit position indicates that status register 1
in port 4 is asserting an interrupt.
Status Register 2, Port 3. A 1 in this bit position indicates that status register 2
in port 3 is asserting an interrupt.
Status Register 1, Port 3. A 1 in this bit position indicates that status register 1
in port 3 is asserting an interrupt.
Status Register 2, Port 2. A 1 in this bit position indicates that status register 2
in port 2 is asserting an interrupt.
Status Register 1, Port 2. A 1 in this bit position indicates that status register 1
in port 2 is asserting an interrupt.
Status Register 2, Port 1. A 1 in this bit position indicates that status register 2
in port 1 is asserting an interrupt.
Status Register 1, Port 1. A 1 in this bit position indicates that status register 1
in port 1 is asserting an interrupt.
Unused
Unused
Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to
within 4 bits of its limit; useful for debugging jitter attenuation operation.
Receive Elastic Store Full. Set when the receive elastic store buffer fills and a
frame is deleted.
Receive Elastic Store Empty. Set when the receive elastic store buffer
empties and a frame is repeated.
CRC Resync Criteria Met. Set when 915/1000 codewords are received in
error.
FAS Resync Criteria Met. Set when three consecutive FAS words are
received in error.
CAS Resync Criteria Met. Set when two consecutive CAS MF alignment
words are received in error.
—
6
6
RIR
Receive Information Register
08 Hex
SR2P3
JALT
5
5
SR1P3
RESF
4
4
28 of 74
SR2P2
RESE
FUNCTION
FUNCTION
3
3
CRCRC
SR1P2
2
2
FASRC
SR2P1
1
1
CASRC
SR1P1
0
0