DS21Q58L+ Maxim Integrated Products, DS21Q58L+ Datasheet - Page 47

• Manufacturer Part Number: DS21Q58L+
• Description: IC TXRX E1 QUAD 3.3V 100LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q58L+

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

21.
The line interface unit contains three sections: the receiver, which handles clock and data recovery; the transmitter,
which waveshapes and drives the E1 line; and the jitter attenuator. The line interface control register (LICR),
described below, controls each of these three sections.
Register Name:
Register Description:
Register Address:
Bit #
Name
21.1 Receive Clock and Data Recovery
The DS21Q58 contains a digital clock recovery system. (See
device couples to the receive E1 shielded twisted pair or coax through a 1:1 transformer
2.048MHz clock attached at the MCLK pin is internally multiplied by 16 through an internal PLL and fed to the clock
recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times oversampler,
which is used to recover the clock and data. This oversampling technique offers outstanding jitter tolerance
(Figure
Normally, RCLK is the recovered clock from the E1 AMI/HDB3 waveform presented at the RTIP and RRING inputs.
When no AMI signal is present at RTIP and RRING, an RCL condition occurs and the RCLK is sourced from the
clock applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, RCLK can
exhibit slightly shorter high cycles of the clock. This is because of the highly oversampled digital clock recovery
circuitry. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator
restores the RCLK to being close to 50% duty cycle. See Receive AC Characteristics in Section
details.
21.1.1 Termination
The DS21Q58 is designed to be fully software-selectable for 75W and 120W termination without the need to change
any external resistors. The user can configure the DS21Q58 for 75W or 120W receive termination by setting the
IRTSEL (CCR5.4) bit. When using the internal termination feature, the external termination resistance should be
120W (typically two 60W resistors). Setting IRTSEL = 1 causes the DS21Q58 to internally apply parallel resistance
to the external resistors to adjust the termination to 75W
JABDS
NAME
TPD
JAS
DJA
L2
L1
L0
—
21-5).
LINE INTERFACE UNIT
L2
7
BIT
7
6
5
4
3
2
1
0
Line Build-Out Select Bit 2. Sets the transmitter build-out.
Line Build-Out Select Bit 1. Sets the transmitter build-out.
Line Build-Out Select Bit 0. Sets the transmitter build-out.
Unused. Should be set = 0 for proper operation.
Jitter Attenuator Select
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select
0 = 128 bits
1 = 32 bits (use for delay-sensitive applications)
Disable Jitter Attenuator
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Transmit Power-Down
0 = powers down the transmitter and tri-states the TTIP and TRING pins
1 = normal transmitter operation
L1
6
LICR
Line Interface Control Register
17 Hex
L0
5
—
4
47 of 74
FUNCTION
(Figure
JAS
3
Figure 3-1
21-3).
JABDS
2
and
DJA
Figure 21-2
1
TPD
0
for more details.) The
(Table
26.4
21-3). The
for more