SAM3A8C Atmel Corporation, SAM3A8C Datasheet - Page 1073

• Manufacturer Part Number: SAM3A8C
• Manufacturer: Atmel Corporation

39.5.1.3
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Interrupts
Figure 39-5. General States
After a hardware reset, the UOTGHS is in the Reset state. In this state:
After writing a one to UOTGHS_CTRL.USBE, the UOTGHS enters the Device or the Host mode
(according to the ID detection) in idle state.
The UOTGHS can be disabled at any time by writing a zero to UOTGHS_CTRL.USBE. In fact,
writing a zero to UOTGHS_CTRL.USBE acts as a hardware reset, except that the
UOTGHS_CTRL.OTGPADE, UOTGHS_CTRL.VBUSPO, UOTGHS_CTRL.FRZCLK,
UOTGHS_CTRL.UIDE, UOTGHS_CTRL.UIMOD and, UOTGHS_DEVCTRL.LS bits are not
reset.
One interrupt vector is assigned to the USB interface.
structure of the USB interrupt system.
• The macro is disabled. The UOTGHS Enable bit in the General Control register
• The macro clock is stopped in order to minimize the power consumption. The Freeze USB
• The UTMI is in suspend mode.
• The internal states and registers of the device and host modes are reset.
• The DPRAM is not cleared and is accessible.
• The UOTGHS_SR.ID and UOTGHS_SR.VBUS bits reflect the states of the UOTGID and
• The OTG Pad Enable (UOTGHS_CTRL.OTGPADE) bit, the VBus Polarity
(UOTGHS_CTRL.USBE) is zero.
Clock bit (UOTGHS_CTRL.FRZCLK) is set.
VBUS input pins.
(UOTGHS_CTRL.VBUSPO) bit, the UOTGHS_CTRL.FRZCLK bit, the
UOTGHS_CTRL.USBE bit, the UOTGID Pin Enable (UOTGHS_CTRL.UIDE) bit, the
UOTGHS Mode (UOTGHS_CTRL.UIMOD) bit, and the Low-Speed Mode Force
(UOTGHS_DEVCTRL.LS) bit can be written by software, so that the user can program pads
and speed before enabling the macro, but their value is only taken into account once the
macro is enabled and unfrozen.
UOTGHS_CTRL.FRZCLK = 1
UOTGHS_CTRL.USBE = 0
Clock stopped:
UOTGHS_CTRL.USBE = 1
Macro off:
Device
ID = 1
UOTGHS_CTRL.USBE = 0
UOTGHS_CTRL.USBE = 1
UOTGHS_CTRL.USBE = 0
Reset
ID = 0
Figure 39-6 on page 1074
UOTGHS_CTRL_USBE = 0
Host
RESET
HW
<any
other
state>
SAM3X/A
SAM3X/A
shows the
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