SAM3A8C Atmel Corporation, SAM3A8C Datasheet - Page 1107

• Manufacturer Part Number: SAM3A8C
• Manufacturer: Atmel Corporation

0: The UOTGHS is disabled.
1: The UOTGHS is enabled.
This bit can be written even if FRZCLK is one.
• FRZCLK: Freeze USB Clock
0: The clock inputs are enabled.
1: The clock inputs are disabled (the resume detection is still active).This reduces the power consumption. Unless explicitly
stated, all registers then become read-only.
This bit can be written even if USBE is zero. Disabling the UOTGHS (by writing a zero to the USBE bit) does not reset this
bit, but this freezes the clock inputs whatever its value.
• VBUSPO: VBus Polarity Off
0: The UOTGVBOF output signal is in its default mode (active high).
1: The UOTGVBOF output signal is inverted (active low).
To be generic. May be useful to control an external VBus power module.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the UOTGHS (by writing a zero to the USBE bit)
does not reset this bit.
• OTGPADE: OTG Pad Enable
0: The OTG pad is disabled.
1: The OTG pad is enabled.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the UOTGHS (by writing a zero to the USBE bit)
does not reset this bit.
• HNPREQ: HNP Request
When the controller is in device mode:
This bit is cleared when the controller has initiated an HNP.
When the controller is in host mode:
• SRPREQ: SRP Request
Writing a one to this bit will initiate an SRP when the controller is in device mode.
Writing a zero to this bit has no effect.
This bit is cleared when the controller has initiated an SRP.
• SRPSEL: SRP Selection
0: Data line pulsing is selected as an SRP method.
1: VBus pulsing is selected as an SRP method.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
• Writing a one to this bit will initiate an HNP (Host Negotiation Protocol).
• Writing a zero to this bit has no effect.
• Writing a one to this bit will accept an HNP.
• Writing a zero to this bit will reject an HNP.
SAM3X/A
SAM3X/A
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