SAM3A8C Atmel Corporation, SAM3A8C Datasheet - Page 55
SAM3A8C
Manufacturer Part Number
SAM3A8C
Description
Manufacturer
Atmel Corporation
- Current page: 55 of 1465
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11.3.1
11.3.2
11.3.3
11.3.4
11.3.4.1
11.3.4.2
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
System level interface
Integrated configurable debug
Cortex-M3 processor features and benefits summary
Cortex-M3 core peripherals
Nested Vectored Interrupt Controller
System control block
The Cortex-M3 processor provides multiple interfaces using AMBA
speed, low latency memory accesses. It supports unaligned data accesses and implements
atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe
Boolean data handling.
The Cortex-M3 processor has a memory protection unit (MPU) that provides fine grain memory
control, enabling applications to implement security privilege levels, separating code, data and
stack on a task-by-task basis. Such requirements are becoming critical in many embedded
applications.
The Cortex-M3 processor implements a complete hardware debug solution. This provides high
system visibility of the processor and memory through either a traditional JTAG port or a 2-pin
Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside
data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system
events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated
messages, data trace, and profiling information through a single pin.
These are:
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that sup-
ports low latency interrupt processing.
The System control block (SCB) is the programmers model interface to the processor. It pro-
vides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
• tight integration of system peripherals reduces area and development costs
• Thumb instruction set combines high code density with 32-bit performance
• code-patch ability for ROM system updates
• power control optimization of system components
• integrated sleep modes for low power consumption
• fast code execution permits slower processor clock or increases sleep mode time
• hardware division and fast multiplier
• deterministic, high-performance interrupt handling for time-critical applications
• memory protection unit (MPU) for safety-critical applications
• extensive debug and trace capabilities:
– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for
debugging and tracing.
®
technology to provide high
SAM3X/A
SAM3X/A
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