SAM3A8C Atmel Corporation, SAM3A8C Datasheet - Page 1095

• Manufacturer Part Number: SAM3A8C
• Manufacturer: Atmel Corporation

39.5.3.3
39.5.3.4
39.5.3.5
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Device Detection
Pipe Reset
USB Reset
minimal power consumption. The USB pad should be in the Idle state. Once a device is con-
nected, the macro enters the Ready state, which does not require the USB clock to be activated.
The controller enters the Suspend state when the USB bus is in a “Suspend” state, i.e., when
the host mode does not generate the “Start of Frame (SOF)”. In this state, the USB consumption
is minimal. The host mode exits the Suspend state when starting to generate the SOF over the
USB line.
A device is detected by the UOTGHS host mode when D+ or D- is no longer tied low, i.e., when
the device D+ or D- pull-up resistor is connected. To enable this detection, the host controller
h a s t o p r o v i d e t h e V B u s p o w e r s u p p l y t o t h e d e v i c e b y w r i t i n g a o n e t o t h e
UOTGHS_SFR.VBUSRQS bit.
The device disconnection is detected by the host controller when both D+ and D- are pulled
down.
The UOTGHS sends a USB bus reset when the user write a one to the Send USB Reset bit in
the Host General Control register (UOTGHS_HSTCTRL.RESET). The USB Reset Sent Interrupt
bit in the Host Global Interrupt Status register (UOTGHS_HSTISR.RSTI) is set when the USB
reset has been sent. In this case, all pipes are disabled and de-allocated.
If the bus was previously in a “Suspend” state (the Start of Frame Generation Enable
(UOTGHS_HSTCTRL.SOFE) bit is zero), the UOTGHS automatically switches to the “Resume”
state, the Host Wake-Up Interrupt (UOTGHS_HSTISR.HWUPI) bit is set and the
UOTGHS_HSTCTRL.SOFE bit is set in order to generate SOFs or micro SOFs immediately
after the USB reset.
At the end of the reset, the user should check the UOTGHS_SR.SPEED field to know the speed
running according to the peripheral capability (LS.FS/HS)
A pipe can be reset at any time by writing a one to the Pipe x Reset (UOTGHS_HSTPIP.PRSTx)
bit. This is recommended before using a pipe upon hardware reset or when a USB bus reset has
been sent. This resets:
The pipe configuration remains active and the pipe is still enabled.
The pipe reset may be associated with a clear of the data toggle sequence. This can be
a c h i e v e d b y s e t t i n g t h e R e s e t D a t a T o g g l e b i t i n t h e P i p e x C o n t r o l r e g i s t e r
(UOTGHS_HSTPIPIMRx.RSTDT) (by writing a one to the Reset Data Toggle Set bit in the Pipe
x Control Set register (UOTGHS_HSTPIPIERx.RSTDTS)).
• the internal state machine of this pipe,
• the receive and transmit bank FIFO counters,
• all the registers of this pipe (UOTGHS_HSTPIPCFGx, UOTGHS_HSTPIPISRx,
UOTGHS_HSTPIPIMRx), except its configuration (UOTGHS_HSTPIPCFGx.ALLOC,
UOTGHS_HSTPIPCFGx.PBK, UOTGHS_HSTPIPCFGx.PSIZE,
UOTGHS_HSTPIPCFGx.PTOKEN, UOTGHS_HSTPIPCFGx.PTYPE,
UOTGHS_HSTPIPCFGx.PEPNUM, UOTGHS_HSTPIPCFGx.INTFRQ) and its Data Toggle
Sequence field (UOTGHS_HSTPIPISRx.DTSEQ).
SAM3X/A
SAM3X/A
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