SAM3A8C Atmel Corporation, SAM3A8C Datasheet - Page 1086

• Manufacturer Part Number: SAM3A8C
• Manufacturer: Atmel Corporation

Figure 39-14. Control Write
Figure 39-15. Control Read
1086
1086
Control read
UOTGHS_DEVEPTISRx. RXOUTI
UOTGHS_DEVEPTISRx.RXSTPI
UOTGHS_DEVEPTISRx.RXOUTI
UOTGHS_DEVEPTISRx RXSTPI
UOTGHS_DEVEPTISRx. TXINI
UOTGHS_DEVEPTISRx.TXINI
SAM3X/A
SAM3X/A
USB Bus
Wr Enable
HOST
Wr Enable
CPU
USB Bus
Figure 39-15 on page 1086
simultaneous write requests from the CPU and the USB host.
A NAK handshake is always generated on the first status stage command.
When the controller detects the status stage, all data written by the CPU is lost and clearing
UOTGHS_DEVEPTISRx.TXINI has no effect.
The user checks if the transmission or the reception is complete.
The OUT retry is always ACKed. This reception sets UOTGHS_DEVEPTISRx.RXOUTI and
UOTGHS_DEVEPTISRx.TXINI. Handle this with the following software algorithm:
Once the OUT status stage has been received, the UOTGHS waits for a SETUP request. The
SETUP request has priority over any other request and has to be ACKed. This means that any
other bit should be cleared and the FIFO reset when a SETUP is received.
set TXINI
wait for RXOUTI OR TXINI
if RXOUTI, then clear bit and return
if TXINI, then continue
SETUP
S
SETUP
E
S
T
HW
E
HW
U
T
P
U
P
SW
SW
SW
shows a control read transaction. The UOTGHS has to manage the
IN
OUT
HW
HW
DATA
SW
DATA
SW
OUT
IN
HW
SW
OUT
NAK
NAK
IN
S
S
SW
T
T
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
A
A
T
T
U
U
S
OUT
S
IN
HW
SW