SAM3A8C Atmel Corporation, SAM3A8C Datasheet - Page 279
SAM3A8C
Manufacturer Part Number
SAM3A8C
Description
Manufacturer
Atmel Corporation
- Current page: 279 of 1465
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Figure 17-4. Supply Monitor Status Bit and Associated Interrupt
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
SMS and SUPC interrupt
Supply Monitor ON
Threshold
A supply monitor detection can either generate a reset of the core power supply or a wake up of
the core power supply. Generating a core reset when a supply monitor detection occurs is
enabled by writing the SMRSTEN bit to 1 in SUPC_SMMR.
Waking up the core power supply when a supply monitor detection occurs can be enabled by
programming the SMEN bit to 1 in the Supply Controller Wake Up Mode Register
(SUPC_WUMR).
The Supply Controller provides two status bits in the Supply Controller Status Register for the
supply monitor which allows to determine whether the last wake up was due to the supply
monitor:
The SMS bit can generate an interrupt if the SMIEN bit is set to 1 in the Supply Controller Supply
Monitor Mode Register (SUPC_SMMR).
3.3 V
• The SMOS bit provides real time information, which is updated at each measurement cycle
• The SMS bit provides saved information and shows a supply monitor detection has occurred
0 V
or updated at each Slow Clock cycle, if the measurement is continuous.
since the last read of SUPC_SR.
Read SUPC_SR
Continuous Sampling (SMSMPL = 1)
Periodic Sampling
SAM3X/A
SAM3X/A
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