SAM3A8C Atmel Corporation, SAM3A8C Datasheet - Page 422
SAM3A8C
Manufacturer Part Number
SAM3A8C
Description
Manufacturer
Atmel Corporation
- Current page: 422 of 1465
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• DS: Drive Strength (only for low-power SDRAM)
DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parame-
ter must be set according to the SDRAM device specification.
After initialization, as soon as DS field is modified and self-refresh mode is activated, the Extended Mode Register is
accessed automatically and DS bits are updated before entry in self-refresh mode. This feature is not supported when
SDRAMC shares an external bus with another controller.
• TIMEOUT: Time to define when low-power mode is enable
Values which are not listed in the table must be considered as “reserved”.
422
422
Value
00
01
10
SAM3X/A
SAM3X/A
LP_LAST_XFER_128
LP_LAST_XFER_64
LP_LAST_XFER
Name
The SDRAM controller activates the SDRAM low-power mode immediately after the end
of the last transfer.
The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the
end of the last transfer.
The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the
end of the last transfer.
Description
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
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