SAM3A8C Atmel Corporation, SAM3A8C Datasheet - Page 411

• Manufacturer Part Number: SAM3A8C
• Manufacturer: Atmel Corporation

Figure 25-5. When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses are not
25.6.5
25.6.5.1
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
SDRAMC_A[12:0]
SDWE
(input)
SDCS
SDCK
DATA
RAS
CAS
Power Management
Row n
Self-refresh Mode
col c col d
delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the device is busy and the
master is held by a wait signal. See
Dnb
Dnc
Three low-power modes are available:
The SDRAM Controller activates one low-power mode as soon as the SDRAM device is not
selected. It is possible to delay the entry in self-refresh and power-down mode after the last
access by programming a timeout value in the Low Power Register.
This mode is selected by programming the LPCB field to 1 in the SDRAMC Low Power Register.
In self-refresh mode, the SDRAM device retains data without external clocking and provides its
own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the SDRAM
device become “don’t care” except SDCKE, which remains low. As soon as the SDRAM device
is selected, the SDRAM Controller provides a sequence of commands and exits self-refresh
mode.
Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter
or all banks of the SDRAM array. This feature reduces the self-refresh current. To configure this
feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self Refresh (PASR)
Dnd
• Self-refresh Mode: The SDRAM executes its own Auto-refresh cycle without control of the
• Power-down Mode: Auto-refresh cycles are controlled by the SDRAM Controller. Between
• Deep Power-down Mode: (Only available with Mobile SDRAM) The SDRAM contents are
SDRAM Controller. Current drained by the SDRAM is very low.
auto-refresh cycles, the SDRAM is in power-down. Current drained in Power-down mode is
higher than in Self-refresh Mode.
lost, but the SDRAM does not drain any current.
t
RP
= 3
Figure
25-5.Refresh Cycle Followed by a Read Access
t
RC
= 8
Row m
t
RCD
= 3
col a
SAM3X/A
SAM3X/A
CAS = 2
Dma
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