SAM3A8C Atmel Corporation, SAM3A8C Datasheet - Page 545

• Manufacturer Part Number: SAM3A8C
• Manufacturer: Atmel Corporation

28.2.8
28.2.9
28.2.10
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Free Running Processor Clock
Programmable Clock Output Controller
Fast Startup
The Free Running Processor Clock (FCLK) used for sampling interrupts and clocking debug
blocks ensures that interrupts can be sampled, and sleep events can be traced, while the pro-
cessor is sleeping. It is connected to Master Clock (MCK).
The PMC controls 3 signals to be output on external pins, PCKx. Each signal can be indepen-
dently programmed via the Programmable Clock Registers (PMC_PCKx).
PCKx can be independently selected between the Slow Clock (SLCK), the Main Clock
(MAINCK), the PLLA Clock (PLLACK), UTMI PLL Clock (UPLLCK/2) and the Master Clock
(MCK) by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a
power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of
PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks
are given in the PCKx bits of PMC_SCSR (System Clock Status Register).
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actu-
ally what has been programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching
clocks, it is strongly recommended to disable the Programmable Clock before any configuration
change and to re-enable it after the change is actually performed.
The device allows the processor to restart in less than 10 microseconds while the device is in
Wait mode. The system enters Wait mode by executing the WaitForEvent (WFE) instruction of
the processor while the LPM bit is at 1 in the PMC Fast Startup Mode Register (PMC_FSMR).
Important: Prior to asserting any WFE instruction to the processor, the internal sources of
wakeup provided by RTT, RTC and USB must be cleared and verified too, that none of the
enabled external wakeup inputs (WKUP) hold an active polarity.
A Fast Startup is enabled upon the detection of a programmed level on one of the 16 wake-up
inputs (WKUP) or upon an active alarm from the RTC, RTT and USB Controller. The polarity of
the 16 wake-up inputs is programmable by writing the PMC Fast Startup Polarity Register
(PMC_FSPR).
The Fast Restart circuitry, as shown in
startup signal to the Power Management Controller. As soon as the fast startup signal is
asserted, the embedded 4/8/12 MHz Fast RC oscillator restarts automatically.
Code Example to select divider 4 for peripheral index 43 (0x2B) and enable its clock:
write_register(PMC_PCR,0x1002102B)
Code Example to read the divider of the same peripheral:
write_register(PMC_PCR,0x0000002B)
read_register(PMC_PCR)
Figure
28-9, is fully asynchronous and provides a fast
SAM3X/A
SAM3X/A
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