AD9146 Analog Devices, AD9146 Datasheet - Page 2

• Manufacturer Part Number: AD9146
• Description: Dual, 16-Bit, 1230 MSPS, TxDAC+® Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9146

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Byte,LVDS,Nibble

AD9146
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Companion Products ....................................................................... 1
Typical Signal Chain......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications ..................................................................................... 5
Absolute Maximum Ratings ............................................................ 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 16
LVDS Input Data Ports .................................................................. 28
Digital Datapath .............................................................................. 32
DC Specifications ......................................................................... 5
Digital Specifications ................................................................... 6
Digital Input Data Timing Specifications ................................. 6
AC Specifications .......................................................................... 7
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Serial Port Operation ................................................................. 16
Data Format ................................................................................ 16
Serial Port Pin Descriptions ...................................................... 16
Serial Port Options ..................................................................... 17
Device Configuration Register Map and Descriptions ......... 18
Byte Interface Mode ................................................................... 28
Nibble Interface Mode ............................................................... 28
FIFO Operation .......................................................................... 28
Interface Timing ......................................................................... 31
Premodulation ............................................................................ 32
Interpolation Filters.................................................................... 32
Datapath Configuration ............................................................ 34
Determining Interpolation Filter Modes ................................ 34
Coarse Modulation Mixing Sequences .................................... 35
Quadrature Phase Correction ................................................... 35
Rev. A | Page 2 of 56
DAC Input Clock Configurations ................................................ 37
Analog Outputs............................................................................... 39
Device Power Management........................................................... 43
Multichip Synchronization ............................................................ 45
Interrupt Request Operation ........................................................ 49
Interface Timing Validation .......................................................... 50
Example Start-Up Routine ............................................................ 52
Outline Dimensions ....................................................................... 53
DC Offset Correction ................................................................ 35
Inverse Sinc Filter ....................................................................... 36
Driving the DACCLK and REFCLK Inputs ........................... 37
Direct Clocking .......................................................................... 37
Clock Multiplication .................................................................. 37
PLL Settings ................................................................................ 38
Configuring the VCO Tuning Band ........................................ 38
Transmit DAC Operation .......................................................... 39
Auxiliary DAC Operation ......................................................... 40
Interfacing to Modulators ......................................................... 41
Baseband Filter Implementation .............................................. 41
Driving the ADL5375-15 .......................................................... 41
Reducing LO Leakage and Unwanted Sidebands .................. 42
Power Dissipation....................................................................... 43
Tx Enable ..................................................................................... 43
Temperature Sensor ................................................................... 44
Synchronization with Clock Multiplication ............................... 45
Synchronization with Direct Clocking .................................... 46
Data Rate Mode Synchronization ............................................ 46
FIFO Rate Mode Synchronization ........................................... 47
Additional Synchronization Features ...................................... 48
Interrupt Service Routine .......................................................... 49
SED Operation ............................................................................ 50
SED Example............................................................................... 51
Device Configuration ................................................................ 52
Derived PLL Settings ................................................................. 52
Start-Up Sequence ...................................................................... 52
Ordering Guide .......................................................................... 53
Data Sheet