AD9146 Analog Devices, AD9146 Datasheet - Page 22

• Manufacturer Part Number: AD9146
• Description: Dual, 16-Bit, 1230 MSPS, TxDAC+® Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9146

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Byte,LVDS,Nibble

AD9146
Register
Name
Clock
Receiver
Control
PLL
Control
PLL Status
Address
(Hex)
0x08
0x0A
0x0C
0x0D
0x0E
0x0F
Bits
7
6
5
4
7
6
[5:0]
[7:6]
[4:0]
[7:6]
4
[3:2]
[1:0]
7
[3:0]
[5:0]
Name
DACCLK duty correction
REFCLK duty correction
DACCLK cross-correction
REFCLK cross-correction
PLL enable
PLL manual enable
Manual VCO Band[5:0]
PLL Loop Bandwidth[1:0]
PLL Charge Pump
Current[4:0]
N2[1:0]
PLL cross-control enable
N0[1:0]
N1[1:0]
PLL locked
VCO Control Voltage[3:0]
VCO Band Readback[5:0]
Rev. A | Page 22 of 56
Description
1 = enable duty cycle correction on the DACCLK input.
1 = enable duty cycle correction on the REFCLK input.
1 = enable differential crossing correction on the DACCLK
input.
1 = enable differential crossing correction on the
REFCLK input.
1 = enable the PLL clock multiplier. The REFCLK input is
used as the PLL reference clock signal.
1 = enable manual selection of the VCO band. The correct
VCO band must be determined by the user and written to
Bits[5:0].
Selects the VCO band to be used.
Selects the PLL loop filter bandwidth.
00 = widest bandwidth.
…
11 = narrowest bandwidth.
Sets the nominal PLL charge pump current.
00000 = lowest current setting.
…
11111 = highest current setting.
PLL control clock divider. This divider determines the ratio
of the DACCLK frequency to the PLL controller clock
frequency. f
00 = f
01 = f
10 = f
11 = f
1 = enable PLL cross-point controller.
PLL VCO divider. This divider determines the ratio of the
VCO frequency to the DACCLK frequency.
00 = f
01 = f
10 = f
11 = f
PLL loop divider. This divider determines the ratio of the
DACCLK frequency to the REFCLK frequency.
00 = f
01 = f
10 = f
11 = f
1 = the PLL-generated clock is tracking the REFCLK input
signal.
VCO control voltage readback. See Table 22.
Indicates the VCO band currently selected.
DACCLK
DACCLK
DACCLK
DACCLK
VCO
VCO
VCO
VCO
DACCLK
DACCLK
DACCLK
DACCLK
/f
/f
/f
/f
DACCLK
DACCLK
DACCLK
DACCLK
/f
/f
/f
/f
/f
/f
/f
/f
PC_CLK
PC_CLK
PC_CLK
PC_CLK
PC_CLK
REFCLK
REFCLK
REFCLK
REFCLK
= 1.
= 2.
= 4.
= 4.
must always be less than 75 MHz.
= 2.
= 4.
= 8.
= 16.
= 2.
= 4.
= 8.
= 16.
Data Sheet
Default
0
0
1
1
0
1
000000
11
10001
11
1
10
01
N/A
N/A
N/A