AD9146 Analog Devices, AD9146 Datasheet - Page 51

• Manufacturer Part Number: AD9146
• Description: Dual, 16-Bit, 1230 MSPS, TxDAC+® Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9146

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Byte,LVDS,Nibble

Data Sheet
SED EXAMPLE
Normal Operation
The following example illustrates the SED configuration for
continuously monitoring the input data and assertion of the
IRQ pin when a single error is detected.
1.
2.
3.
Load the following comparison values. (Comparison values
can be chosen arbitrarily; however, choosing values that
require frequent bit toggling provides the most robust test.)
Register 0x68: I
Register 0x69: I
Register 0x6A: Q
Register 0x6B: Q
Register 0x6C: I
Register 0x6D: I
Register 0x6E: Q
Register 0x6F: Q
Enable the SED error detect flag to assert the IRQ pin.
(Set Register 0x05 to 0x04.)
Begin transmitting the input data pattern.
0LSB
0MSB
1LSB
1MSB
1MSB
0MSB
1LSB
0LSB
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4.
5.
If IRQ is asserted, read Register 0x67 and Register 0x70 through
Register 0x73 to verify that a SED error was detected and to deter-
mine which input bits were in error. The bits in Register 0x70
through Register 0x73 are latched; therefore, the bits indicate
any errors that occurred on those bits throughout the test (not
only the errors that caused the error detected flag to be set).
Enabling the alignment of the I0 sample as described in the
SED Operation section requires the use of the FRAME signal.
The timing diagrams for byte and nibble modes are the same
as during normal operation and are shown in Figure 33 and
Figure 34, respectively.
Write to Register 0x67 to enable the SED.
(Set Register 0x67 to 0x80.)
Clear the SED errors in Register 0x67 and Register 0x07.
When the SED is first turned on, the FRAME signal may
be detected immediately; therefore, the SED failure bit may
be asserted due to the unknown initial FRAME status. For
this reason, the SED compare fail status bit must be cleared
at least once immediately after enabling the SED.
AD9146