AD9146 Analog Devices, AD9146 Datasheet - Page 25

• Manufacturer Part Number: AD9146
• Description: Dual, 16-Bit, 1230 MSPS, TxDAC+® Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9146

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Byte,LVDS,Nibble

Data Sheet
Register
Name
Datapath
Config
Chip ID
I Phase Adj
LSB
I Phase Adj
MSB
Q Phase Adj
LSB
Q Phase Adj
MSB
I DAC Offset
LSB
I DAC Offset
MSB
Q DAC
Offset LSB
Q DAC
Offset MSB
I DAC
FS Adjust
I DAC
Control
I Aux DAC
Data
I Aux DAC
Control
Q DAC
FS Adjust
Address
(Hex)
0x1E
0x1F
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
Bits
0
[7:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
7
[1:0]
[7:0]
7
6
5
[1:0]
[7:0]
Name
Set to 1
Chip ID[7:0]
I Phase Adj[7:0]
I Phase Adj[9:8]
Q Phase Adj[7:0]
Q Phase Adj[9:8]
I DAC Offset[7:0]
I DAC Offset[15:8]
Q DAC Offset[7:0]
Q DAC Offset[15:8]
I DAC FS Adj[7:0]
I DAC sleep
I DAC FS Adj[9:8]
I Aux DAC[7:0]
I aux DAC sign
I aux DAC current
direction
I aux DAC sleep
I Aux DAC[9:8]
Q DAC FS Adj[7:0]
Rev. A | Page 25 of 56
Description
Set this bit to 1 for proper operation. (The default value
must be changed from 0 to 1.)
This register identifies the device as an AD9146.
See Register 0x39.
I Phase Adj[9:0] is used to insert a phase offset between
the I and Q datapaths. This offset can be used to correct
for phase imbalance in a quadrature modulator. See the
Quadrature Phase Correction section for more information.
See Register 0x3B.
Q Phase Adj[9:0] is used to insert a phase offset between
the I and Q datapaths. This offset can be used to correct
for phase imbalance in a quadrature modulator. See the
Quadrature Phase Correction section for more information.
See Register 0x3D.
I DAC Offset[15:0] is a value that is added directly to the
samples written to the I DAC.
See Register 0x3F.
Q DAC Offset[15:0] is a value that is added directly to the
samples written to the Q DAC.
See Register 0x41, Bits[1:0].
1 = puts the I DAC into sleep mode (fast wake-up mode).
I DAC FS Adj[9:0] sets the full-scale current of the I DAC.
The full-scale current can be adjusted from 8.64 mA to
31.68 mA in step sizes of approximately 22.5 µA.
0x000 = 8.64 mA.
…
0x200 = 20.16 mA.
…
0x3FF = 31.68 mA.
See Register 0x43, Bits[1:0].
0 = the I auxiliary DAC sign is positive, and the current is
directed to the IOUT1P pin (Pin 47).
1 = the I auxiliary DAC sign is negative, and the current is
directed to the IOUT1N pin (Pin 46).
0 = the I auxiliary DAC sources current.
1 = the I auxiliary DAC sinks current.
1 = puts the I auxiliary DAC into sleep mode.
I Aux DAC[9:0] sets the magnitude of the auxiliary DAC
current. The range is 0 mA to 2 mA, and the step size is 2 µA.
0x000 = 0.000 mA.
0x001 = 0.002 mA.
…
0x3FF = 2.046 mA.
See Register 0x45, Bits[1:0].
Default
0
00001000
00000000
00
00000000
00
00000000
00000000
00000000
00000000
11111001
0
01
00000000
0
0
0
00
11111001
AD9146