AD9146 Analog Devices, AD9146 Datasheet - Page 29

• Manufacturer Part Number: AD9146
• Description: Dual, 16-Bit, 1230 MSPS, TxDAC+® Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9146

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Byte,LVDS,Nibble

Data Sheet
Nominally, data is written to and read from the FIFO at the same
rate. This keeps the FIFO depth constant. If data is written to the
FIFO faster than data is read out, the FIFO depth increases. If
data is read out of the FIFO faster than data is written to it, the
FIFO depth decreases. For optimum timing margin, the FIFO
depth should be maintained near half full (a difference of 4
between the write pointer and read pointer values). The FIFO
depth represents the FIFO pipeline delay and is part of the
overall latency of the AD9146.
Resetting the FIFO
When the AD9146 is powered on, the FIFO depth is unknown.
To avoid a concurrent read and write to the same FIFO address
and to ensure a fixed pipeline delay, it is important to reset the
FIFO pointers to known states. The FIFO pointers can be initial-
ized in two ways: via a write sequence to the serial port or by
strobing the FRAME input.
There are two types of FIFO reset: a relative reset and an absolute
reset. A relative reset enforces a defined FIFO depth. An absolute
reset enforces a particular write pointer value when the reset is
initiated. A serial port initiated FIFO reset is always a relative
reset. A FRAME strobe initiated reset can be either a relative or
an absolute reset.
The operation of the FRAME initiated FIFO reset depends on
the synchronization mode chosen.


For more information about the synchronization function, see
the Multichip Synchronization section.
When synchronization is disabled or when it is configured
for data rate mode synchronization, the FRAME strobe
initiates a relative FIFO reset. The reference point of the
relative reset is the position of the read pointer.
When FIFO mode synchronization is chosen, the FRAME
strobe initiates an absolute FIFO reset.
FIFO SOFT ALIGN REQUEST
FRAME
DATA
DCI
LATCH
INPUT
REG 0x18[1]
FORMAT
DATA
DATA/FIFO RATE
Figure 32. Block Diagram of FIFO
32
POINTER
REG 0x10[6]
WRITE
Rev. A | Page 29 of 56
32 BITS
RESET
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
LOGIC
FIFO PHASE OFFSET
REG 0x17[2:0]
A summary of the synchronization modes and the types of
FIFO reset used is provided in Table 13.
Table 13. Summary of FIFO Resets
FIFO Reset Signal
Serial Port
FRAME
For a FRAME dependent FIFO reset to occur, an extended
FRAME pulse must be sent to the part for proper operation.
The extended FRAME pulse must be asserted high for an entire
I and Q DAC data sample load. This corresponds to four data
clock samples in byte mode and eight data clock samples in
nibble mode (see Figure 33 and Figure 34, respectively).
EXTENDED
EXTENDED
POINTER
FRAME
FRAME
READ
DATA
[15:0]
DATA
[15:0]
Figure 34. Timing Diagram for Extended Frame Pulse (Nibble Mode)
Figure 33. Timing Diagram for Extended Frame Pulse (Byte Mode)
DCI
DCI
32
Q
Q
0LSB
0N0
I AND Q
PATHS
DATA
I
÷ INT
1MSB
I
1N3
32
I
I
1N2
1LSB
Disabled
Relative
Relative
I AND Q
DACS
Q
I
1N1
1MSB
DACCLK
SYNC
Synchronization Mode
I
1N0
Q
1LSB
Data Rate
Relative
Relative
Q
1N3
I
2MSB
Q
1N2
I
2LSB
Q
1N1
Q
AD9146
FIFO Reset
Relative
Absolute
2MSB
Q
1N0
Q
2LSB
I
2N3