AD9146 Analog Devices, AD9146 Datasheet - Page 52

• Manufacturer Part Number: AD9146
• Description: Dual, 16-Bit, 1230 MSPS, TxDAC+® Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9146

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Byte,LVDS,Nibble

AD9146
EXAMPLE START-UP ROUTINE
To ensure reliable start-up of the AD9146, certain sequences
should be followed. This section shows an example start-up
routine. This example uses the configuration described in the
Device Configuration section.
DEVICE CONFIGURATION
The following device configuration is used for this example.
•
•
•
•
•
•
•
•
DERIVED PLL SETTINGS
The following PLL settings can be derived from the device
configuration.
•
•
•
•
START-UP SEQUENCE
The following sequence configures the power clock and register
write sequencing for reliable device start-up.
Power up Device (no specific power supply
sequence is required)
Apply stable REFCLK input signal.
Apply stable DCI input signal.
f
Interpolation is 4×, using HB1 = 10 and HB2 = 010010
Input data is baseband data
f
f
PLL is enabled
Inverse sinc filter is enabled
Synchronization is enabled
f
f
N1 = f
N2 = f
DATA
OUT
REFCLK
DACCLK
VCO
= 140 MHz
= 4 × f
= 122.88 MSPS
DACCLK
VCO
= 122.88 MHz
= f
/f
DATA
DACCLK
DACCLK
/f
REFCLK
× interpolation = 491.52 MHz
= 1966.08 MHz (1 GHz < f
= 4
= 4
VCO
< 2 GHz)
Rev. A | Page 52 of 56
Device Configuration Register Write Sequence:
0x00  0x20 /* Issue Software Reset */
0x00  0x80 /* Enable 3-wire SPI */
0x1E  0x01
/* Start PLL */
0x0C  0xE1
0x0D  0xD9
0x0A  0xCF
0x0A  0xA0
/* Verify PLL is Locked */
Read 0x0E
Read 0x06
0x10  0x48 /* Choose Data Rate Mode */
0x17  0x04 /* Issue Software FIFO Reset */
0x18  0x02
0x18  0x00
/* Verify FIFO Reset */
Read 0x18
Read 0x19
0x1B  0xA4 /* Enable Inverse Sinc */
/* Configure Interpolation Filters */
0x1C  0x04
0x1D  0x24
/* Expect bit 7 = 0, bit 6 = 1 */
/* Expect 0x5C */
/* Expect 0x05 */
/* Expect 0x07 */
Data Sheet