AD9146 Analog Devices, AD9146 Datasheet - Page 28

• Manufacturer Part Number: AD9146
• Description: Dual, 16-Bit, 1230 MSPS, TxDAC+® Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9146

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Byte,LVDS,Nibble

AD9146
LVDS INPUT DATA PORTS
The AD9146 has one LVDS data port that receives data for both
the I and Q transmit paths. The device can accept data in byte
and nibble formats. In byte and nibble modes, the data is sent
over 8-bit and 4-bit LVDS data buses, respectively. The pin
assignments of the bus in each mode are shown in Table 12.
Table 12. Data Bit Pair Assignments for Data Input Modes
Mode
Byte
Nibble
1
The data is accompanied by DCI and FRAME signals. The DCI
signal is a reference bit that is used to generate a double data rate
(DDR) clock. The FRAME signal is required for controlling to
which DAC the data is sent. All of the interface signals can be time
aligned, so there is a maximum skew requirement on the bus. In
some cases, it is best to delay the DCI signal for optimum timing.
BYTE INTERFACE MODE
In byte mode, the DCI signal is a reference bit used to generate
the data sampling clock and should be time aligned with the data.
The most significant byte of the data should correspond to DCI
high, and the least significant byte of the data should correspond to
DCI low. The FRAME signal indicates to which DAC the data
is sent. When FRAME is high, data is sent to the I DAC; when
FRAME is low, data is sent to the Q DAC. The complete timing
diagram is shown in Figure 30.
NIBBLE INTERFACE MODE
In nibble mode, the DCI signal is a reference bit used to generate
the data sampling clock and should be time aligned with the data.
The FRAME signal indicates to which DAC the data is sent.
In nibble mode, the unused pins can be left floating.
1
MSB to LSB
D7, D6, D5, D4, D3, D2, D1, D0
D5, D4, D3, D2
DATA[15:0]
DATA[15:0]
FRAME
FRAME
DCI
DCI
Q
Q
0N0
0LSB
I
1N3
I
1MSB
Figure 31. Timing Diagram for Nibble Mode
Figure 30. Timing Diagram for Byte Mode
I
1N2
I
1LSB
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I
1N1
Q
1MSB
I
1N0
Q
1LSB
Q
When FRAME is high, data is sent to the I DAC; when FRAME
is low, data is sent to the Q DAC. All four nibbles must be written
to the device for proper operation. For 12-bit resolution devices,
the data in the fourth nibble acts as a placeholder for the data
framing structure. The complete timing diagram is shown in
Figure 31.
FIFO OPERATION
The AD9146 contains a 2-channel, 16-bit wide, eight-word deep
FIFO designed to relax the timing relationship between the data
arriving at the DAC input ports and the internal DAC data rate
clock. The FIFO acts as a buffer that absorbs timing variations
between the data source and the DAC, such as the clock-to-data
variation of an FPGA or ASIC, which significantly increases the
timing budget of the interface.
Figure 32 shows the block diagram of the datapath through the
FIFO. The data is latched into the device, is formatted, and is
then written into the FIFO register determined by the FIFO write
pointer. The value of the write pointer is incremented every time a
new word is loaded into the FIFO. Meanwhile, data is read from
the FIFO register determined by the read pointer and fed into
the digital datapath. The value of the read pointer is incremented
every time data is read into the datapath from the FIFO. The FIFO
pointers are incremented at the data rate (DACCLK rate divided by
the interpolation ratio).
Valid data is transmitted through the FIFO as long as the
FIFO does not overflow or become empty. An overflow or
empty condition of the FIFO occurs when the write pointer and
read pointer point to the same FIFO location. This simultan-
eous access of data leads to unreliable data transfer through
the FIFO and must be avoided.
1N3
I
2MSB
Q
1N2
I
2LSB
Q
1N1
Q
2MSB
Q
1N0
Q
2LSB
I
2N3
Data Sheet