AD9146 Analog Devices, AD9146 Datasheet - Page 21

• Manufacturer Part Number: AD9146
• Description: Dual, 16-Bit, 1230 MSPS, TxDAC+® Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9146

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Byte,LVDS,Nibble

Data Sheet
Register
Name
Data Format
Interrupt
Enable
Event Flag
Address
(Hex)
0x03
0x04
0x05
0x06
0x07
Bits
7
6
5
[1:0]
7
6
5
4
1
0
[7:5]
4
3
2
[1:0]
7
6
5
4
1
0
4
3
2
Name
Binary data format
Q data first
MSB swap
Data Bus Width[1:0]
Enable PLL lock lost
Enable PLL locked
Enable sync signal lost
Enable sync signal locked
Enable FIFO Warning 1
Enable FIFO Warning 2
Set to 0
Enable AED compare pass
Enable AED compare fail
Enable SED compare fail
Set to 0
PLL lock lost
PLL locked
Sync signal lost
Sync signal locked
FIFO Warning 1
FIFO Warning 2
Note that all event flags are cleared by writing the respective bit high.
AED compare pass
AED compare fail
SED compare fail
Note that all event flags are cleared by writing the respective bit high.
Rev. A | Page 21 of 56
1 = indicates that the SED logic detected a valid input data
pattern compared against the preprogrammed expected
values. This is a latched signal.
1 = indicates that the SED logic detected an invalid input data
pattern compared against the preprogrammed expected
values. This latched signal is automatically cleared when
eight valid I/Q data pairs are received.
1 = indicates that the SED logic detected an invalid input
data pattern compared against the preprogrammed
expected values. This is a latched signal.
Description
0 = input data is in twos complement format.
1 = input data is in binary format.
Indicates I/Q data pairing on data input.
0 = I data sent to data receiver first.
1 = Q data sent to data receiver first.
Swaps the bit order of the data input port.
0 = order of the data bits corresponds to the pin descriptions.
1 = bit designations are swapped; most significant bits
become the least significant bits.
Data receiver interface mode. See the LVDS Input Data Ports
section for information about the operation of the different
interface modes.
00 = byte mode; 8-bit interface bus width.
01 = byte mode; 8-bit interface bus width.
10 = nibble mode; 4-bit interface bus width.
11 = invalid.
1 = enable interrupt for PLL lock lost.
1 = enable interrupt for PLL locked.
1 = enable interrupt for sync signal lost.
1 = enable interrupt for sync signal locked.
1 = enable interrupt for FIFO Warning 1.
1 = enable interrupt for FIFO Warning 2.
Set these bits to 0.
1 = enable interrupt for AED comparison pass.
1 = enable interrupt for AED comparison fail.
1 = enable interrupt for SED comparison fail.
Set these bits to 0.
1 = indicates that the PLL, which had been previously
locked, has unlocked from the reference signal. This is a
latched signal.
1 = indicates that the PLL has locked to the reference
clock input.
1 = indicates that the sync logic, which had been previously
locked, has lost alignment. This is a latched signal.
1 = indicates that the sync logic has achieved sync
alignment. This is indicated when no phase changes
were requested for at least a few full averaging cycles.
1 = indicates that the difference between the FIFO read
and write pointers is 1.
1 = indicates that the difference between the FIFO read
and write pointers is 2.
Default
0
0
0
00
0
0
0
0
0
0
000
0
0
0
00
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
AD9146