ST72361AR9-Auto STMicroelectronics, ST72361AR9-Auto Datasheet - Page 114

• Manufacturer Part Number: ST72361AR9-Auto
• Description: 8-bit MCU for automotive with K Flash, 10-bit ADC, 5 Timers, SPI, 2x LINSCI
• Manufacturer: STMicroelectronics

Specifications of ST72361AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

16-bit timer
114/279
Procedure
To use Pulse Width Modulation mode:
1.
2.
3.
4.
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OC
the following formula:
Where:
t
f
PRESC
If the timer clock is an external clock the formula is:
Where:
t
CPU
Load the OC2R register with the value corresponding to the period of the signal using
the formula in the opposite column.
Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column.
Select the following in the CR1 register:
–
–
Select the following in the CR2 register:
–
–
–
=
=
=
i
R register value required for a specific timing application can be calculated using
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register.
Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
Set the PWM bit.
Select the timer clock (CC[1:0]) (see
Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see
= Signal or pulse period (in seconds)
CPU clock frequency (in hertz)
Signal or pulse period (in seconds)
Doc ID 12468 Rev 3
Counter
= OC1R
Counter
= OC2R
When
When
OCiR Value =
OCiR =
Pulse Width Modulation cycle
t
*
OCMP1 = OLVL2
f
OCMP1 = OLVL1
Counter is reset
EXT
Table
ICF1 bit is set
PRESC
t
*
to FFFCh
f
CPU
-5
50).
- 5
ST72361xx-Auto
Table
50)